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-rw-r--r--target-ppc/op_helper.c1522
1 files changed, 976 insertions, 546 deletions
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 8bb93ed36..1ea16951b 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -18,7 +18,9 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "exec.h"
+#include "host-utils.h"
+#include "helper_regs.h"
#include "op_helper.h"
#define MEMSUFFIX _raw
@@ -31,6 +33,9 @@
#define MEMSUFFIX _kernel
#include "op_helper.h"
#include "op_helper_mem.h"
+#define MEMSUFFIX _hypv
+#include "op_helper.h"
+#include "op_helper_mem.h"
#endif
//#define DEBUG_OP
@@ -45,14 +50,6 @@ void do_raise_exception_err (uint32_t exception, int error_code)
#if 0
printf("Raise exception %3x code : %d\n", exception, error_code);
#endif
- switch (exception) {
- case POWERPC_EXCP_PROGRAM:
- if (error_code == POWERPC_EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
- return;
- break;
- default:
- break;
- }
env->exception_index = exception;
env->error_code = error_code;
cpu_loop_exit();
@@ -93,24 +90,6 @@ void do_store_cr (uint32_t mask)
}
}
-void do_load_xer (void)
-{
- T0 = (xer_so << XER_SO) |
- (xer_ov << XER_OV) |
- (xer_ca << XER_CA) |
- (xer_bc << XER_BC) |
- (xer_cmp << XER_CMP);
-}
-
-void do_store_xer (void)
-{
- xer_so = (T0 >> XER_SO) & 0x01;
- xer_ov = (T0 >> XER_OV) & 0x01;
- xer_ca = (T0 >> XER_CA) & 0x01;
- xer_cmp = (T0 >> XER_CMP) & 0xFF;
- xer_bc = (T0 >> XER_BC) & 0x7F;
-}
-
#if defined(TARGET_PPC64)
void do_store_pri (int prio)
{
@@ -119,77 +98,6 @@ void do_store_pri (int prio)
}
#endif
-void do_load_fpscr (void)
-{
- /* The 32 MSB of the target fpr are undefined.
- * They'll be zero...
- */
- union {
- float64 d;
- struct {
- uint32_t u[2];
- } s;
- } u;
- int i;
-
-#if defined(WORDS_BIGENDIAN)
-#define WORD0 0
-#define WORD1 1
-#else
-#define WORD0 1
-#define WORD1 0
-#endif
- u.s.u[WORD0] = 0;
- u.s.u[WORD1] = 0;
- for (i = 0; i < 8; i++)
- u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
- FT0 = u.d;
-}
-
-void do_store_fpscr (uint32_t mask)
-{
- /*
- * We use only the 32 LSB of the incoming fpr
- */
- union {
- double d;
- struct {
- uint32_t u[2];
- } s;
- } u;
- int i, rnd_type;
-
- u.d = FT0;
- if (mask & 0x80)
- env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
- for (i = 1; i < 7; i++) {
- if (mask & (1 << (7 - i)))
- env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
- }
- /* TODO: update FEX & VX */
- /* Set rounding mode */
- switch (env->fpscr[0] & 0x3) {
- case 0:
- /* Best approximation (round to nearest) */
- rnd_type = float_round_nearest_even;
- break;
- case 1:
- /* Smaller magnitude (round toward zero) */
- rnd_type = float_round_to_zero;
- break;
- case 2:
- /* Round toward +infinite */
- rnd_type = float_round_up;
- break;
- default:
- case 3:
- /* Round toward -infinite */
- rnd_type = float_round_down;
- break;
- }
- set_float_rounding_mode(rnd_type, &env->fp_status);
-}
-
target_ulong ppc_load_dump_spr (int sprn)
{
if (loglevel != 0) {
@@ -211,79 +119,6 @@ void ppc_store_dump_spr (int sprn, target_ulong val)
/*****************************************************************************/
/* Fixed point operations helpers */
-#if defined(TARGET_PPC64)
-static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
-{
- *plow += a;
- /* carry test */
- if (*plow < a)
- (*phigh)++;
- *phigh += b;
-}
-
-static void neg128 (uint64_t *plow, uint64_t *phigh)
-{
- *plow = ~*plow;
- *phigh = ~*phigh;
- add128(plow, phigh, 1, 0);
-}
-
-static void mul64 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
-{
- uint32_t a0, a1, b0, b1;
- uint64_t v;
-
- a0 = a;
- a1 = a >> 32;
-
- b0 = b;
- b1 = b >> 32;
-
- v = (uint64_t)a0 * (uint64_t)b0;
- *plow = v;
- *phigh = 0;
-
- v = (uint64_t)a0 * (uint64_t)b1;
- add128(plow, phigh, v << 32, v >> 32);
-
- v = (uint64_t)a1 * (uint64_t)b0;
- add128(plow, phigh, v << 32, v >> 32);
-
- v = (uint64_t)a1 * (uint64_t)b1;
- *phigh += v;
-#if defined(DEBUG_MULDIV)
- printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
- a, b, *phigh, *plow);
-#endif
-}
-
-void do_mul64 (uint64_t *plow, uint64_t *phigh)
-{
- mul64(plow, phigh, T0, T1);
-}
-
-static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
-{
- int sa, sb;
-
- sa = (a < 0);
- if (sa)
- a = -a;
- sb = (b < 0);
- if (sb)
- b = -b;
- mul64(plow, phigh, a, b);
- if (sa ^ sb) {
- neg128(plow, phigh);
- }
-}
-
-void do_imul64 (uint64_t *plow, uint64_t *phigh)
-{
- imul64(plow, phigh, T0, T1);
-}
-#endif
-
void do_adde (void)
{
T2 = T0;
@@ -314,15 +149,12 @@ void do_addmeo (void)
{
T1 = T0;
T0 += xer_ca + (-1);
- if (likely(!((uint32_t)T1 &
- ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
+ xer_ov = ((uint32_t)T1 & ((uint32_t)T1 ^ (uint32_t)T0)) >> 31;
+ xer_so |= xer_ov;
if (likely(T1 != 0))
xer_ca = 1;
+ else
+ xer_ca = 0;
}
#if defined(TARGET_PPC64)
@@ -330,43 +162,40 @@ void do_addmeo_64 (void)
{
T1 = T0;
T0 += xer_ca + (-1);
- if (likely(!((uint64_t)T1 &
- ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
+ xer_ov = ((uint64_t)T1 & ((uint64_t)T1 ^ (uint64_t)T0)) >> 63;
+ xer_so |= xer_ov;
if (likely(T1 != 0))
xer_ca = 1;
+ else
+ xer_ca = 0;
}
#endif
void do_divwo (void)
{
- if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
+ if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
(int32_t)T1 == 0))) {
xer_ov = 0;
T0 = (int32_t)T0 / (int32_t)T1;
} else {
xer_ov = 1;
- xer_so = 1;
- T0 = (-1) * ((uint32_t)T0 >> 31);
+ T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
}
+ xer_so |= xer_ov;
}
#if defined(TARGET_PPC64)
void do_divdo (void)
{
- if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
+ if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == (int64_t)-1LL) ||
(int64_t)T1 == 0))) {
xer_ov = 0;
T0 = (int64_t)T0 / (int64_t)T1;
} else {
xer_ov = 1;
- xer_so = 1;
- T0 = (-1ULL) * ((uint64_t)T0 >> 63);
+ T0 = UINT64_MAX * ((uint64_t)T0 >> 63);
}
+ xer_so |= xer_ov;
}
#endif
@@ -415,14 +244,15 @@ void do_mulldo (void)
int64_t th;
uint64_t tl;
- do_imul64(&tl, &th);
- if (likely(th == 0)) {
+ muls64(&tl, &th, T0, T1);
+ T0 = (int64_t)tl;
+ /* If th != 0 && th != -1, then we had an overflow */
+ if (likely((uint64_t)(th + 1) <= 1)) {
xer_ov = 0;
} else {
xer_ov = 1;
- xer_so = 1;
}
- T0 = (int64_t)tl;
+ xer_so |= xer_ov;
}
#endif
@@ -478,15 +308,12 @@ void do_subfmeo (void)
{
T1 = T0;
T0 = ~T0 + xer_ca - 1;
- if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
- (1UL << 31)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
+ xer_ov = ((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0)) >> 31;
+ xer_so |= xer_ov;
if (likely((uint32_t)T1 != UINT32_MAX))
xer_ca = 1;
+ else
+ xer_ca = 0;
}
#if defined(TARGET_PPC64)
@@ -494,15 +321,12 @@ void do_subfmeo_64 (void)
{
T1 = T0;
T0 = ~T0 + xer_ca - 1;
- if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
- (1ULL << 63)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
+ xer_ov = ((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0)) >> 63;
+ xer_so |= xer_ov;
if (likely((uint64_t)T1 != UINT64_MAX))
xer_ca = 1;
+ else
+ xer_ca = 0;
}
#endif
@@ -510,13 +334,9 @@ void do_subfzeo (void)
{
T1 = T0;
T0 = ~T0 + xer_ca;
- if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
- ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
+ xer_ov = (((uint32_t)~T1 ^ UINT32_MAX) &
+ ((uint32_t)(~T1) ^ (uint32_t)T0)) >> 31;
+ xer_so |= xer_ov;
if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
xer_ca = 0;
} else {
@@ -529,13 +349,9 @@ void do_subfzeo_64 (void)
{
T1 = T0;
T0 = ~T0 + xer_ca;
- if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
- ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
+ xer_ov = (((uint64_t)~T1 ^ UINT64_MAX) &
+ ((uint64_t)(~T1) ^ (uint64_t)T0)) >> 63;
+ xer_so |= xer_ov;
if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
xer_ca = 0;
} else {
@@ -544,6 +360,18 @@ void do_subfzeo_64 (void)
}
#endif
+void do_cntlzw (void)
+{
+ T0 = clz32(T0);
+}
+
+#if defined(TARGET_PPC64)
+void do_cntlzd (void)
+{
+ T0 = clz64(T0);
+}
+#endif
+
/* shift right arithmetic helper */
void do_sraw (void)
{
@@ -562,7 +390,7 @@ void do_sraw (void)
xer_ca = 0;
}
} else {
- ret = (-1) * ((uint32_t)T0 >> 31);
+ ret = UINT32_MAX * ((uint32_t)T0 >> 31);
if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
xer_ca = 0;
} else {
@@ -590,7 +418,7 @@ void do_srad (void)
xer_ca = 0;
}
} else {
- ret = (-1) * ((uint64_t)T0 >> 63);
+ ret = UINT64_MAX * ((uint64_t)T0 >> 63);
if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
xer_ca = 0;
} else {
@@ -601,16 +429,6 @@ void do_srad (void)
}
#endif
-static inline int popcnt (uint32_t val)
-{
- int i;
-
- for (i = 0; val != 0;)
- val = val ^ (val - 1);
-
- return i;
-}
-
void do_popcntb (void)
{
uint32_t ret;
@@ -618,7 +436,7 @@ void do_popcntb (void)
ret = 0;
for (i = 0; i < 32; i += 8)
- ret |= popcnt((T0 >> i) & 0xFF) << i;
+ ret |= ctpop8((T0 >> i) & 0xFF) << i;
T0 = ret;
}
@@ -630,13 +448,544 @@ void do_popcntb_64 (void)
ret = 0;
for (i = 0; i < 64; i += 8)
- ret |= popcnt((T0 >> i) & 0xFF) << i;
+ ret |= ctpop8((T0 >> i) & 0xFF) << i;
T0 = ret;
}
#endif
/*****************************************************************************/
/* Floating point operations helpers */
+static always_inline int fpisneg (float64 f)
+{
+ union {
+ float64 f;
+ uint64_t u;
+ } u;
+
+ u.f = f;
+
+ return u.u >> 63 != 0;
+}
+
+static always_inline int isden (float f)
+{
+ union {
+ float64 f;
+ uint64_t u;
+ } u;
+
+ u.f = f;
+
+ return ((u.u >> 52) & 0x7FF) == 0;
+}
+
+static always_inline int iszero (float64 f)
+{
+ union {
+ float64 f;
+ uint64_t u;
+ } u;
+
+ u.f = f;
+
+ return (u.u & ~0x8000000000000000ULL) == 0;
+}
+
+static always_inline int isinfinity (float64 f)
+{
+ union {
+ float64 f;
+ uint64_t u;
+ } u;
+
+ u.f = f;
+
+ return ((u.u >> 52) & 0x7FF) == 0x7FF &&
+ (u.u & 0x000FFFFFFFFFFFFFULL) == 0;
+}
+
+void do_compute_fprf (int set_fprf)
+{
+ int isneg;
+
+ isneg = fpisneg(FT0);
+ if (unlikely(float64_is_nan(FT0))) {
+ if (float64_is_signaling_nan(FT0)) {
+ /* Signaling NaN: flags are undefined */
+ T0 = 0x00;
+ } else {
+ /* Quiet NaN */
+ T0 = 0x11;
+ }
+ } else if (unlikely(isinfinity(FT0))) {
+ /* +/- infinity */
+ if (isneg)
+ T0 = 0x09;
+ else
+ T0 = 0x05;
+ } else {
+ if (iszero(FT0)) {
+ /* +/- zero */
+ if (isneg)
+ T0 = 0x12;
+ else
+ T0 = 0x02;
+ } else {
+ if (isden(FT0)) {
+ /* Denormalized numbers */
+ T0 = 0x10;
+ } else {
+ /* Normalized numbers */
+ T0 = 0x00;
+ }
+ if (isneg) {
+ T0 |= 0x08;
+ } else {
+ T0 |= 0x04;
+ }
+ }
+ }
+ if (set_fprf) {
+ /* We update FPSCR_FPRF */
+ env->fpscr &= ~(0x1F << FPSCR_FPRF);
+ env->fpscr |= T0 << FPSCR_FPRF;
+ }
+ /* We just need fpcc to update Rc1 */
+ T0 &= 0xF;
+}
+
+/* Floating-point invalid operations exception */
+static always_inline void fload_invalid_op_excp (int op)
+{
+ int ve;
+
+ ve = fpscr_ve;
+ if (op & POWERPC_EXCP_FP_VXSNAN) {
+ /* Operation on signaling NaN */
+ env->fpscr |= 1 << FPSCR_VXSNAN;
+ }
+ if (op & POWERPC_EXCP_FP_VXSOFT) {
+ /* Software-defined condition */
+ env->fpscr |= 1 << FPSCR_VXSOFT;
+ }
+ switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
+ case POWERPC_EXCP_FP_VXISI:
+ /* Magnitude subtraction of infinities */
+ env->fpscr |= 1 << FPSCR_VXISI;
+ goto update_arith;
+ case POWERPC_EXCP_FP_VXIDI:
+ /* Division of infinity by infinity */
+ env->fpscr |= 1 << FPSCR_VXIDI;
+ goto update_arith;
+ case POWERPC_EXCP_FP_VXZDZ:
+ /* Division of zero by zero */
+ env->fpscr |= 1 << FPSCR_VXZDZ;
+ goto update_arith;
+ case POWERPC_EXCP_FP_VXIMZ:
+ /* Multiplication of zero by infinity */
+ env->fpscr |= 1 << FPSCR_VXIMZ;
+ goto update_arith;
+ case POWERPC_EXCP_FP_VXVC:
+ /* Ordered comparison of NaN */
+ env->fpscr |= 1 << FPSCR_VXVC;
+ env->fpscr &= ~(0xF << FPSCR_FPCC);
+ env->fpscr |= 0x11 << FPSCR_FPCC;
+ /* We must update the target FPR before raising the exception */
+ if (ve != 0) {
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* Exception is differed */
+ ve = 0;
+ }
+ break;
+ case POWERPC_EXCP_FP_VXSQRT:
+ /* Square root of a negative number */
+ env->fpscr |= 1 << FPSCR_VXSQRT;
+ update_arith:
+ env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
+ if (ve == 0) {
+ /* Set the result to quiet NaN */
+ FT0 = UINT64_MAX;
+ env->fpscr &= ~(0xF << FPSCR_FPCC);
+ env->fpscr |= 0x11 << FPSCR_FPCC;
+ }
+ break;
+ case POWERPC_EXCP_FP_VXCVI:
+ /* Invalid conversion */
+ env->fpscr |= 1 << FPSCR_VXCVI;
+ env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
+ if (ve == 0) {
+ /* Set the result to quiet NaN */
+ FT0 = UINT64_MAX;
+ env->fpscr &= ~(0xF << FPSCR_FPCC);
+ env->fpscr |= 0x11 << FPSCR_FPCC;
+ }
+ break;
+ }
+ /* Update the floating-point invalid operation summary */
+ env->fpscr |= 1 << FPSCR_VX;
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (ve != 0) {
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ if (msr_fe0 != 0 || msr_fe1 != 0)
+ do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
+ }
+}
+
+static always_inline void float_zero_divide_excp (void)
+{
+ union {
+ float64 f;
+ uint64_t u;
+ } u0, u1;
+
+ env->fpscr |= 1 << FPSCR_ZX;
+ env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ze != 0) {
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ if (msr_fe0 != 0 || msr_fe1 != 0) {
+ do_raise_exception_err(POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
+ }
+ } else {
+ /* Set the result to infinity */
+ u0.f = FT0;
+ u1.f = FT1;
+ u0.u = ((u0.u ^ u1.u) & 0x8000000000000000ULL);
+ u0.u |= 0x7FFULL << 52;
+ FT0 = u0.f;
+ }
+}
+
+static always_inline void float_overflow_excp (void)
+{
+ env->fpscr |= 1 << FPSCR_OX;
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_oe != 0) {
+ /* XXX: should adjust the result */
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* We must update the target FPR before raising the exception */
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
+ } else {
+ env->fpscr |= 1 << FPSCR_XX;
+ env->fpscr |= 1 << FPSCR_FI;
+ }
+}
+
+static always_inline void float_underflow_excp (void)
+{
+ env->fpscr |= 1 << FPSCR_UX;
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ue != 0) {
+ /* XXX: should adjust the result */
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* We must update the target FPR before raising the exception */
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
+ }
+}
+
+static always_inline void float_inexact_excp (void)
+{
+ env->fpscr |= 1 << FPSCR_XX;
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_xe != 0) {
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* We must update the target FPR before raising the exception */
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
+ }
+}
+
+static always_inline void fpscr_set_rounding_mode (void)
+{
+ int rnd_type;
+
+ /* Set rounding mode */
+ switch (fpscr_rn) {
+ case 0:
+ /* Best approximation (round to nearest) */
+ rnd_type = float_round_nearest_even;
+ break;
+ case 1:
+ /* Smaller magnitude (round toward zero) */
+ rnd_type = float_round_to_zero;
+ break;
+ case 2:
+ /* Round toward +infinite */
+ rnd_type = float_round_up;
+ break;
+ default:
+ case 3:
+ /* Round toward -infinite */
+ rnd_type = float_round_down;
+ break;
+ }
+ set_float_rounding_mode(rnd_type, &env->fp_status);
+}
+
+void do_fpscr_setbit (int bit)
+{
+ int prev;
+
+ prev = (env->fpscr >> bit) & 1;
+ env->fpscr |= 1 << bit;
+ if (prev == 0) {
+ switch (bit) {
+ case FPSCR_VX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ve)
+ goto raise_ve;
+ case FPSCR_OX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_oe)
+ goto raise_oe;
+ break;
+ case FPSCR_UX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ue)
+ goto raise_ue;
+ break;
+ case FPSCR_ZX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ze)
+ goto raise_ze;
+ break;
+ case FPSCR_XX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_xe)
+ goto raise_xe;
+ break;
+ case FPSCR_VXSNAN:
+ case FPSCR_VXISI:
+ case FPSCR_VXIDI:
+ case FPSCR_VXZDZ:
+ case FPSCR_VXIMZ:
+ case FPSCR_VXVC:
+ case FPSCR_VXSOFT:
+ case FPSCR_VXSQRT:
+ case FPSCR_VXCVI:
+ env->fpscr |= 1 << FPSCR_VX;
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ve != 0)
+ goto raise_ve;
+ break;
+ case FPSCR_VE:
+ if (fpscr_vx != 0) {
+ raise_ve:
+ env->error_code = POWERPC_EXCP_FP;
+ if (fpscr_vxsnan)
+ env->error_code |= POWERPC_EXCP_FP_VXSNAN;
+ if (fpscr_vxisi)
+ env->error_code |= POWERPC_EXCP_FP_VXISI;
+ if (fpscr_vxidi)
+ env->error_code |= POWERPC_EXCP_FP_VXIDI;
+ if (fpscr_vxzdz)
+ env->error_code |= POWERPC_EXCP_FP_VXZDZ;
+ if (fpscr_vximz)
+ env->error_code |= POWERPC_EXCP_FP_VXIMZ;
+ if (fpscr_vxvc)
+ env->error_code |= POWERPC_EXCP_FP_VXVC;
+ if (fpscr_vxsoft)
+ env->error_code |= POWERPC_EXCP_FP_VXSOFT;
+ if (fpscr_vxsqrt)
+ env->error_code |= POWERPC_EXCP_FP_VXSQRT;
+ if (fpscr_vxcvi)
+ env->error_code |= POWERPC_EXCP_FP_VXCVI;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_OE:
+ if (fpscr_ox != 0) {
+ raise_oe:
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_UE:
+ if (fpscr_ux != 0) {
+ raise_ue:
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_ZE:
+ if (fpscr_zx != 0) {
+ raise_ze:
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_XE:
+ if (fpscr_xx != 0) {
+ raise_xe:
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_RN1:
+ case FPSCR_RN:
+ fpscr_set_rounding_mode();
+ break;
+ default:
+ break;
+ raise_excp:
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* We have to update Rc1 before raising the exception */
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ break;
+ }
+ }
+}
+
+#if defined(WORDS_BIGENDIAN)
+#define WORD0 0
+#define WORD1 1
+#else
+#define WORD0 1
+#define WORD1 0
+#endif
+void do_store_fpscr (uint32_t mask)
+{
+ /*
+ * We use only the 32 LSB of the incoming fpr
+ */
+ union {
+ double d;
+ struct {
+ uint32_t u[2];
+ } s;
+ } u;
+ uint32_t prev, new;
+ int i;
+
+ u.d = FT0;
+ prev = env->fpscr;
+ new = u.s.u[WORD1];
+ new &= ~0x90000000;
+ new |= prev & 0x90000000;
+ for (i = 0; i < 7; i++) {
+ if (mask & (1 << i)) {
+ env->fpscr &= ~(0xF << (4 * i));
+ env->fpscr |= new & (0xF << (4 * i));
+ }
+ }
+ /* Update VX and FEX */
+ if (fpscr_ix != 0)
+ env->fpscr |= 1 << FPSCR_VX;
+ if ((fpscr_ex & fpscr_eex) != 0) {
+ env->fpscr |= 1 << FPSCR_FEX;
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ /* XXX: we should compute it properly */
+ env->error_code = POWERPC_EXCP_FP;
+ }
+ fpscr_set_rounding_mode();
+}
+#undef WORD0
+#undef WORD1
+
+#ifdef CONFIG_SOFTFLOAT
+void do_float_check_status (void)
+{
+ if (env->exception_index == POWERPC_EXCP_PROGRAM &&
+ (env->error_code & POWERPC_EXCP_FP)) {
+ /* Differred floating-point exception after target FPR update */
+ if (msr_fe0 != 0 || msr_fe1 != 0)
+ do_raise_exception_err(env->exception_index, env->error_code);
+ } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
+ float_overflow_excp();
+ } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
+ float_underflow_excp();
+ } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
+ float_inexact_excp();
+ }
+}
+#endif
+
+#if USE_PRECISE_EMULATION
+void do_fadd (void)
+{
+ if (unlikely(float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1))) {
+ /* sNaN addition */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (likely(isfinite(FT0) || isfinite(FT1) ||
+ fpisneg(FT0) == fpisneg(FT1))) {
+ FT0 = float64_add(FT0, FT1, &env->fp_status);
+ } else {
+ /* Magnitude subtraction of infinities */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
+ }
+}
+
+void do_fsub (void)
+{
+ if (unlikely(float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1))) {
+ /* sNaN subtraction */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (likely(isfinite(FT0) || isfinite(FT1) ||
+ fpisneg(FT0) != fpisneg(FT1))) {
+ FT0 = float64_sub(FT0, FT1, &env->fp_status);
+ } else {
+ /* Magnitude subtraction of infinities */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
+ }
+}
+
+void do_fmul (void)
+{
+ if (unlikely(float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1))) {
+ /* sNaN multiplication */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
+ (iszero(FT0) && isinfinity(FT1)))) {
+ /* Multiplication of zero by infinity */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
+ } else {
+ FT0 = float64_mul(FT0, FT1, &env->fp_status);
+ }
+}
+
+void do_fdiv (void)
+{
+ if (unlikely(float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1))) {
+ /* sNaN division */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
+ /* Division of infinity by infinity */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
+ } else if (unlikely(iszero(FT1))) {
+ if (iszero(FT0)) {
+ /* Division of zero by zero */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
+ } else {
+ /* Division by zero */
+ float_zero_divide_excp();
+ }
+ } else {
+ FT0 = float64_div(FT0, FT1, &env->fp_status);
+ }
+}
+#endif /* USE_PRECISE_EMULATION */
+
void do_fctiw (void)
{
union {
@@ -644,14 +993,22 @@ void do_fctiw (void)
uint64_t i;
} p;
- p.i = float64_to_int32(FT0, &env->fp_status);
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN conversion */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ /* qNan / infinity conversion */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ } else {
+ p.i = float64_to_int32(FT0, &env->fp_status);
#if USE_PRECISE_EMULATION
- /* XXX: higher bits are not supposed to be significant.
- * to make tests easier, return the same as a real PowerPC 750 (aka G3)
- */
- p.i |= 0xFFF80000ULL << 32;
+ /* XXX: higher bits are not supposed to be significant.
+ * to make tests easier, return the same as a real PowerPC 750
+ */
+ p.i |= 0xFFF80000ULL << 32;
#endif
- FT0 = p.d;
+ FT0 = p.d;
+ }
}
void do_fctiwz (void)
@@ -661,14 +1018,22 @@ void do_fctiwz (void)
uint64_t i;
} p;
- p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN conversion */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ /* qNan / infinity conversion */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ } else {
+ p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
#if USE_PRECISE_EMULATION
- /* XXX: higher bits are not supposed to be significant.
- * to make tests easier, return the same as a real PowerPC 750 (aka G3)
- */
- p.i |= 0xFFF80000ULL << 32;
+ /* XXX: higher bits are not supposed to be significant.
+ * to make tests easier, return the same as a real PowerPC 750
+ */
+ p.i |= 0xFFF80000ULL << 32;
#endif
- FT0 = p.d;
+ FT0 = p.d;
+ }
}
#if defined(TARGET_PPC64)
@@ -690,8 +1055,16 @@ void do_fctid (void)
uint64_t i;
} p;
- p.i = float64_to_int64(FT0, &env->fp_status);
- FT0 = p.d;
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN conversion */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ /* qNan / infinity conversion */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ } else {
+ p.i = float64_to_int64(FT0, &env->fp_status);
+ FT0 = p.d;
+ }
}
void do_fctidz (void)
@@ -701,20 +1074,34 @@ void do_fctidz (void)
uint64_t i;
} p;
- p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
- FT0 = p.d;
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN conversion */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ /* qNan / infinity conversion */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ } else {
+ p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
+ FT0 = p.d;
+ }
}
#endif
-static inline void do_fri (int rounding_mode)
+static always_inline void do_fri (int rounding_mode)
{
- int curmode;
-
- curmode = env->fp_status.float_rounding_mode;
- set_float_rounding_mode(rounding_mode, &env->fp_status);
- FT0 = float64_round_to_int(FT0, &env->fp_status);
- set_float_rounding_mode(curmode, &env->fp_status);
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN round */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ /* qNan / infinity round */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ } else {
+ set_float_rounding_mode(rounding_mode, &env->fp_status);
+ FT0 = float64_round_to_int(FT0, &env->fp_status);
+ /* Restore rounding mode from FPSCR */
+ fpscr_set_rounding_mode();
+ }
}
void do_frin (void)
@@ -740,90 +1127,142 @@ void do_frim (void)
#if USE_PRECISE_EMULATION
void do_fmadd (void)
{
+ if (unlikely(float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1) ||
+ float64_is_signaling_nan(FT2))) {
+ /* sNaN operation */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else {
#ifdef FLOAT128
- float128 ft0_128, ft1_128;
-
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
- ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
- ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
+ /* This is the way the PowerPC specification defines it */
+ float128 ft0_128, ft1_128;
+
+ ft0_128 = float64_to_float128(FT0, &env->fp_status);
+ ft1_128 = float64_to_float128(FT1, &env->fp_status);
+ ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
+ ft1_128 = float64_to_float128(FT2, &env->fp_status);
+ ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
+ FT0 = float128_to_float64(ft0_128, &env->fp_status);
#else
- /* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) + FT2;
+ /* This is OK on x86 hosts */
+ FT0 = (FT0 * FT1) + FT2;
#endif
+ }
}
void do_fmsub (void)
{
+ if (unlikely(float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1) ||
+ float64_is_signaling_nan(FT2))) {
+ /* sNaN operation */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else {
#ifdef FLOAT128
- float128 ft0_128, ft1_128;
-
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
- ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
- ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
+ /* This is the way the PowerPC specification defines it */
+ float128 ft0_128, ft1_128;
+
+ ft0_128 = float64_to_float128(FT0, &env->fp_status);
+ ft1_128 = float64_to_float128(FT1, &env->fp_status);
+ ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
+ ft1_128 = float64_to_float128(FT2, &env->fp_status);
+ ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
+ FT0 = float128_to_float64(ft0_128, &env->fp_status);
#else
- /* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) - FT2;
+ /* This is OK on x86 hosts */
+ FT0 = (FT0 * FT1) - FT2;
#endif
+ }
}
#endif /* USE_PRECISE_EMULATION */
void do_fnmadd (void)
{
+ if (unlikely(float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1) ||
+ float64_is_signaling_nan(FT2))) {
+ /* sNaN operation */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else {
#if USE_PRECISE_EMULATION
#ifdef FLOAT128
- float128 ft0_128, ft1_128;
-
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
- ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
- ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
+ /* This is the way the PowerPC specification defines it */
+ float128 ft0_128, ft1_128;
+
+ ft0_128 = float64_to_float128(FT0, &env->fp_status);
+ ft1_128 = float64_to_float128(FT1, &env->fp_status);
+ ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
+ ft1_128 = float64_to_float128(FT2, &env->fp_status);
+ ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
+ FT0 = float128_to_float64(ft0_128, &env->fp_status);
#else
- /* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) + FT2;
+ /* This is OK on x86 hosts */
+ FT0 = (FT0 * FT1) + FT2;
#endif
#else
- FT0 = float64_mul(FT0, FT1, &env->fp_status);
- FT0 = float64_add(FT0, FT2, &env->fp_status);
+ FT0 = float64_mul(FT0, FT1, &env->fp_status);
+ FT0 = float64_add(FT0, FT2, &env->fp_status);
#endif
- if (likely(!isnan(FT0)))
- FT0 = float64_chs(FT0);
+ if (likely(!isnan(FT0)))
+ FT0 = float64_chs(FT0);
+ }
}
void do_fnmsub (void)
{
+ if (unlikely(float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1) ||
+ float64_is_signaling_nan(FT2))) {
+ /* sNaN operation */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else {
#if USE_PRECISE_EMULATION
#ifdef FLOAT128
- float128 ft0_128, ft1_128;
-
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
- ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
- ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
+ /* This is the way the PowerPC specification defines it */
+ float128 ft0_128, ft1_128;
+
+ ft0_128 = float64_to_float128(FT0, &env->fp_status);
+ ft1_128 = float64_to_float128(FT1, &env->fp_status);
+ ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
+ ft1_128 = float64_to_float128(FT2, &env->fp_status);
+ ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
+ FT0 = float128_to_float64(ft0_128, &env->fp_status);
#else
- /* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) - FT2;
+ /* This is OK on x86 hosts */
+ FT0 = (FT0 * FT1) - FT2;
#endif
#else
- FT0 = float64_mul(FT0, FT1, &env->fp_status);
- FT0 = float64_sub(FT0, FT2, &env->fp_status);
+ FT0 = float64_mul(FT0, FT1, &env->fp_status);
+ FT0 = float64_sub(FT0, FT2, &env->fp_status);
#endif
- if (likely(!isnan(FT0)))
- FT0 = float64_chs(FT0);
+ if (likely(!isnan(FT0)))
+ FT0 = float64_chs(FT0);
+ }
}
+#if USE_PRECISE_EMULATION
+void do_frsp (void)
+{
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN square root */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else {
+ FT0 = float64_to_float32(FT0, &env->fp_status);
+ }
+}
+#endif /* USE_PRECISE_EMULATION */
+
void do_fsqrt (void)
{
- FT0 = float64_sqrt(FT0, &env->fp_status);
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN square root */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
+ /* Square root of a negative nonzero number */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
+ } else {
+ FT0 = float64_sqrt(FT0, &env->fp_status);
+ }
}
void do_fre (void)
@@ -833,7 +1272,13 @@ void do_fre (void)
uint64_t i;
} p;
- if (likely(isnormal(FT0))) {
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN reciprocal */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(iszero(FT0))) {
+ /* Zero reciprocal */
+ float_zero_divide_excp();
+ } else if (likely(isnormal(FT0))) {
FT0 = float64_div(1.0, FT0, &env->fp_status);
} else {
p.d = FT0;
@@ -843,7 +1288,7 @@ void do_fre (void)
p.i = 0x7FF0000000000000ULL;
} else if (isnan(FT0)) {
p.i = 0x7FF8000000000000ULL;
- } else if (FT0 < 0.0) {
+ } else if (fpisneg(FT0)) {
p.i = 0x8000000000000000ULL;
} else {
p.i = 0x0000000000000000ULL;
@@ -859,7 +1304,13 @@ void do_fres (void)
uint64_t i;
} p;
- if (likely(isnormal(FT0))) {
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN reciprocal */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(iszero(FT0))) {
+ /* Zero reciprocal */
+ float_zero_divide_excp();
+ } else if (likely(isnormal(FT0))) {
#if USE_PRECISE_EMULATION
FT0 = float64_div(1.0, FT0, &env->fp_status);
FT0 = float64_to_float32(FT0, &env->fp_status);
@@ -874,7 +1325,7 @@ void do_fres (void)
p.i = 0x7FF0000000000000ULL;
} else if (isnan(FT0)) {
p.i = 0x7FF8000000000000ULL;
- } else if (FT0 < 0.0) {
+ } else if (fpisneg(FT0)) {
p.i = 0x8000000000000000ULL;
} else {
p.i = 0x0000000000000000ULL;
@@ -890,7 +1341,13 @@ void do_frsqrte (void)
uint64_t i;
} p;
- if (likely(isnormal(FT0) && FT0 > 0.0)) {
+ if (unlikely(float64_is_signaling_nan(FT0))) {
+ /* sNaN reciprocal square root */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
+ /* Reciprocal square root of a negative nonzero number */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
+ } else if (likely(isnormal(FT0))) {
FT0 = float64_sqrt(FT0, &env->fp_status);
FT0 = float32_div(1.0, FT0, &env->fp_status);
} else {
@@ -900,9 +1357,8 @@ void do_frsqrte (void)
} else if (p.i == 0x0000000000000000ULL) {
p.i = 0x7FF0000000000000ULL;
} else if (isnan(FT0)) {
- if (!(p.i & 0x0008000000000000ULL))
- p.i |= 0x000FFFFFFFFFFFFFULL;
- } else if (FT0 < 0) {
+ p.i |= 0x000FFFFFFFFFFFFFULL;
+ } else if (fpisneg(FT0)) {
p.i = 0x7FF8000000000000ULL;
} else {
p.i = 0x0000000000000000ULL;
@@ -913,7 +1369,7 @@ void do_frsqrte (void)
void do_fsel (void)
{
- if (FT0 >= 0)
+ if (!fpisneg(FT0) || iszero(FT0))
FT0 = FT1;
else
FT0 = FT2;
@@ -921,7 +1377,11 @@ void do_fsel (void)
void do_fcmpu (void)
{
- if (likely(!isnan(FT0) && !isnan(FT1))) {
+ if (unlikely(float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1))) {
+ /* sNaN comparison */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else {
if (float64_lt(FT0, FT1, &env->fp_status)) {
T0 = 0x08UL;
} else if (!float64_le(FT0, FT1, &env->fp_status)) {
@@ -929,18 +1389,25 @@ void do_fcmpu (void)
} else {
T0 = 0x02UL;
}
- } else {
- T0 = 0x01UL;
- env->fpscr[4] |= 0x1;
- env->fpscr[6] |= 0x1;
}
- env->fpscr[3] = T0;
+ env->fpscr &= ~(0x0F << FPSCR_FPRF);
+ env->fpscr |= T0 << FPSCR_FPRF;
}
void do_fcmpo (void)
{
- env->fpscr[4] &= ~0x1;
- if (likely(!isnan(FT0) && !isnan(FT1))) {
+ if (unlikely(float64_is_nan(FT0) ||
+ float64_is_nan(FT1))) {
+ if (float64_is_signaling_nan(FT0) ||
+ float64_is_signaling_nan(FT1)) {
+ /* sNaN comparison */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
+ POWERPC_EXCP_FP_VXVC);
+ } else {
+ /* qNaN comparison */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
+ }
+ } else {
if (float64_lt(FT0, FT1, &env->fp_status)) {
T0 = 0x08UL;
} else if (!float64_le(FT0, FT1, &env->fp_status)) {
@@ -948,73 +1415,69 @@ void do_fcmpo (void)
} else {
T0 = 0x02UL;
}
- } else {
- T0 = 0x01UL;
- env->fpscr[4] |= 0x1;
- if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) {
- /* Quiet NaN case */
- env->fpscr[6] |= 0x1;
- if (!(env->fpscr[1] & 0x8))
- env->fpscr[4] |= 0x8;
- } else {
- env->fpscr[4] |= 0x8;
- }
}
- env->fpscr[3] = T0;
+ env->fpscr &= ~(0x0F << FPSCR_FPRF);
+ env->fpscr |= T0 << FPSCR_FPRF;
}
#if !defined (CONFIG_USER_ONLY)
void cpu_dump_rfi (target_ulong RA, target_ulong msr);
-void do_rfi (void)
+
+void do_store_msr (void)
+{
+ T0 = hreg_store_msr(env, T0, 0);
+ if (T0 != 0) {
+ env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ do_raise_exception(T0);
+ }
+}
+
+static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
+ target_ulong msrm, int keep_msrh)
{
#if defined(TARGET_PPC64)
- if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
- env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
- do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
+ if (msr & (1ULL << MSR_SF)) {
+ nip = (uint64_t)nip;
+ msr &= (uint64_t)msrm;
} else {
- env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
- ppc_store_msr_32(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
+ nip = (uint32_t)nip;
+ msr = (uint32_t)(msr & msrm);
+ if (keep_msrh)
+ msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
}
#else
- env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
- do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
+ nip = (uint32_t)nip;
+ msr &= (uint32_t)msrm;
#endif
+ /* XXX: beware: this is false if VLE is supported */
+ env->nip = nip & ~((target_ulong)0x00000003);
+ hreg_store_msr(env, msr, 1);
#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
+ cpu_dump_rfi(env->nip, env->msr);
#endif
+ /* No need to raise an exception here,
+ * as rfi is always the last insn of a TB
+ */
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
+void do_rfi (void)
+{
+ __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
+ ~((target_ulong)0xFFFF0000), 1);
+}
+
#if defined(TARGET_PPC64)
void do_rfid (void)
{
- if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
- env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
- do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
- } else {
- env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
- do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
- }
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
+ ~((target_ulong)0xFFFF0000), 0);
}
-#endif
-#if defined(TARGET_PPC64H)
+
void do_hrfid (void)
{
- if (env->spr[SPR_HSRR1] & (1ULL << MSR_SF)) {
- env->nip = (uint64_t)(env->spr[SPR_HSRR0] & ~0x00000003);
- do_store_msr(env, (uint64_t)(env->spr[SPR_HSRR1] & ~0xFFFF0000UL));
- } else {
- env->nip = (uint32_t)(env->spr[SPR_HSRR0] & ~0x00000003);
- do_store_msr(env, (uint32_t)(env->spr[SPR_HSRR1] & ~0xFFFF0000UL));
- }
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
+ ~((target_ulong)0xFFFF0000), 0);
}
#endif
#endif
@@ -1046,14 +1509,16 @@ void do_td (int flags)
/* PowerPC 601 specific instructions (POWER bridge) */
void do_POWER_abso (void)
{
- if ((uint32_t)T0 == INT32_MIN) {
+ if ((int32_t)T0 == INT32_MIN) {
T0 = INT32_MAX;
xer_ov = 1;
- xer_so = 1;
- } else {
+ } else if ((int32_t)T0 < 0) {
T0 = -T0;
xer_ov = 0;
+ } else {
+ xer_ov = 0;
}
+ xer_so |= xer_ov;
}
void do_POWER_clcs (void)
@@ -1061,21 +1526,21 @@ void do_POWER_clcs (void)
switch (T0) {
case 0x0CUL:
/* Instruction cache line size */
- T0 = ICACHE_LINE_SIZE;
+ T0 = env->icache_line_size;
break;
case 0x0DUL:
/* Data cache line size */
- T0 = DCACHE_LINE_SIZE;
+ T0 = env->dcache_line_size;
break;
case 0x0EUL:
/* Minimum cache line size */
- T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
- ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
+ T0 = env->icache_line_size < env->dcache_line_size ?
+ env->icache_line_size : env->dcache_line_size;
break;
case 0x0FUL:
/* Maximum cache line size */
- T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
- ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
+ T0 = env->icache_line_size > env->dcache_line_size ?
+ env->icache_line_size : env->dcache_line_size;
break;
default:
/* Undefined */
@@ -1087,8 +1552,9 @@ void do_POWER_div (void)
{
uint64_t tmp;
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
+ if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
+ (int32_t)T1 == 0) {
+ T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
env->spr[SPR_MQ] = 0;
} else {
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
@@ -1101,29 +1567,30 @@ void do_POWER_divo (void)
{
int64_t tmp;
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
+ if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
+ (int32_t)T1 == 0) {
+ T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
env->spr[SPR_MQ] = 0;
xer_ov = 1;
- xer_so = 1;
} else {
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
env->spr[SPR_MQ] = tmp % T1;
tmp /= (int32_t)T1;
if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
xer_ov = 1;
- xer_so = 1;
} else {
xer_ov = 0;
}
T0 = tmp;
}
+ xer_so |= xer_ov;
}
void do_POWER_divs (void)
{
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
+ if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
+ (int32_t)T1 == 0) {
+ T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
env->spr[SPR_MQ] = 0;
} else {
env->spr[SPR_MQ] = T0 % T1;
@@ -1133,16 +1600,17 @@ void do_POWER_divs (void)
void do_POWER_divso (void)
{
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
+ if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
+ (int32_t)T1 == 0) {
+ T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
env->spr[SPR_MQ] = 0;
xer_ov = 1;
- xer_so = 1;
} else {
T0 = (int32_t)T0 / (int32_t)T1;
env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
xer_ov = 0;
}
+ xer_so |= xer_ov;
}
void do_POWER_dozo (void)
@@ -1168,10 +1636,10 @@ void do_POWER_maskg (void)
uint32_t ret;
if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
- ret = -1;
+ ret = UINT32_MAX;
} else {
- ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
- (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
+ ret = (UINT32_MAX >> ((uint32_t)T0)) ^
+ ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
if ((uint32_t)T0 > (uint32_t)T1)
ret = ~ret;
}
@@ -1196,34 +1664,42 @@ void do_POWER_mulo (void)
#if !defined (CONFIG_USER_ONLY)
void do_POWER_rac (void)
{
-#if 0
mmu_ctx_t ctx;
+ int nb_BATs;
/* We don't have to generate many instances of this instruction,
* as rac is supervisor only.
*/
- if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
+ /* XXX: FIX THIS: Pretend we have no BAT */
+ nb_BATs = env->nb_BATs;
+ env->nb_BATs = 0;
+ if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
T0 = ctx.raddr;
-#endif
+ env->nb_BATs = nb_BATs;
}
void do_POWER_rfsvc (void)
{
- env->nip = env->lr & ~0x00000003UL;
- T0 = env->ctr & 0x0000FFFFUL;
- do_store_msr(env, T0);
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
}
-/* PowerPC 601 BAT management helper */
-void do_store_601_batu (int nr)
+void do_store_hid0_601 (void)
{
- do_store_ibatu(env, nr, (uint32_t)T0);
- env->DBAT[0][nr] = env->IBAT[0][nr];
- env->DBAT[1][nr] = env->IBAT[1][nr];
+ uint32_t hid0;
+
+ hid0 = env->spr[SPR_HID0];
+ if ((T0 ^ hid0) & 0x00000008) {
+ /* Change current endianness */
+ env->hflags &= ~(1 << MSR_LE);
+ env->hflags_nmsr &= ~(1 << MSR_LE);
+ env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
+ env->hflags |= env->hflags_nmsr;
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
+ __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
+ }
+ }
+ env->spr[SPR_HID0] = T0;
}
#endif
@@ -1261,17 +1737,6 @@ void do_op_602_mfrom (void)
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
-void do_405_check_ov (void)
-{
- if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
- !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
-}
-
void do_405_check_sat (void)
{
if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
@@ -1327,63 +1792,26 @@ void do_store_dcr (void)
#if !defined(CONFIG_USER_ONLY)
void do_40x_rfci (void)
{
- env->nip = env->spr[SPR_40x_SRR2];
- do_store_msr(env, env->spr[SPR_40x_SRR3] & ~0xFFFF0000);
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request = CPU_INTERRUPT_EXITTB;
+ __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
+ ~((target_ulong)0xFFFF0000), 0);
}
void do_rfci (void)
{
-#if defined(TARGET_PPC64)
- if (env->spr[SPR_BOOKE_CSRR1] & (1 << MSR_CM)) {
- env->nip = (uint64_t)env->spr[SPR_BOOKE_CSRR0];
- } else
-#endif
- {
- env->nip = (uint32_t)env->spr[SPR_BOOKE_CSRR0];
- }
- do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_CSRR1] & ~0x3FFF0000);
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request = CPU_INTERRUPT_EXITTB;
+ __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
+ ~((target_ulong)0x3FFF0000), 0);
}
void do_rfdi (void)
{
-#if defined(TARGET_PPC64)
- if (env->spr[SPR_BOOKE_DSRR1] & (1 << MSR_CM)) {
- env->nip = (uint64_t)env->spr[SPR_BOOKE_DSRR0];
- } else
-#endif
- {
- env->nip = (uint32_t)env->spr[SPR_BOOKE_DSRR0];
- }
- do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_DSRR1] & ~0x3FFF0000);
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request = CPU_INTERRUPT_EXITTB;
+ __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
+ ~((target_ulong)0x3FFF0000), 0);
}
void do_rfmci (void)
{
-#if defined(TARGET_PPC64)
- if (env->spr[SPR_BOOKE_MCSRR1] & (1 << MSR_CM)) {
- env->nip = (uint64_t)env->spr[SPR_BOOKE_MCSRR0];
- } else
-#endif
- {
- env->nip = (uint32_t)env->spr[SPR_BOOKE_MCSRR0];
- }
- do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_MCSRR1] & ~0x3FFF0000);
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request = CPU_INTERRUPT_EXITTB;
+ __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
+ ~((target_ulong)0x3FFF0000), 0);
}
void do_load_403_pb (int num)
@@ -1422,7 +1850,6 @@ void do_440_dlmzb (void)
T0 = i;
}
-#if defined(TARGET_PPCEMB)
/* SPE extension helpers */
/* Use a table to make this quicker */
static uint8_t hbrev[16] = {
@@ -1430,27 +1857,27 @@ static uint8_t hbrev[16] = {
0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
};
-static inline uint8_t byte_reverse (uint8_t val)
+static always_inline uint8_t byte_reverse (uint8_t val)
{
return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
}
-static inline uint32_t word_reverse (uint32_t val)
+static always_inline uint32_t word_reverse (uint32_t val)
{
return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
(byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
}
-#define MASKBITS 16 // Random value - to be fixed
+#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
void do_brinc (void)
{
uint32_t a, b, d, mask;
- mask = (uint32_t)(-1UL) >> MASKBITS;
- b = T1_64 & mask;
- a = T0_64 & mask;
- d = word_reverse(1 + word_reverse(a | ~mask));
- T0_64 = (T0_64 & ~mask) | (d & mask);
+ mask = UINT32_MAX >> (32 - MASKBITS);
+ a = T0 & mask;
+ b = T1 & mask;
+ d = word_reverse(1 + word_reverse(a | ~b));
+ T0 = (T0 & ~mask) | (d & b);
}
#define DO_SPE_OP2(name) \
@@ -1468,69 +1895,69 @@ void do_ev##name (void) \
}
/* Fixed-point vector arithmetic */
-static inline uint32_t _do_eabs (uint32_t val)
+static always_inline uint32_t _do_eabs (uint32_t val)
{
- if (val != 0x80000000)
- val &= ~0x80000000;
+ if ((val & 0x80000000) && val != 0x80000000)
+ val -= val;
return val;
}
-static inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
+static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
{
return op1 + op2;
}
-static inline int _do_ecntlsw (uint32_t val)
+static always_inline int _do_ecntlsw (uint32_t val)
{
if (val & 0x80000000)
- return _do_cntlzw(~val);
+ return clz32(~val);
else
- return _do_cntlzw(val);
+ return clz32(val);
}
-static inline int _do_ecntlzw (uint32_t val)
+static always_inline int _do_ecntlzw (uint32_t val)
{
- return _do_cntlzw(val);
+ return clz32(val);
}
-static inline uint32_t _do_eneg (uint32_t val)
+static always_inline uint32_t _do_eneg (uint32_t val)
{
if (val != 0x80000000)
- val ^= 0x80000000;
+ val -= val;
return val;
}
-static inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
+static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
{
return rotl32(op1, op2);
}
-static inline uint32_t _do_erndw (uint32_t val)
+static always_inline uint32_t _do_erndw (uint32_t val)
{
return (val + 0x000080000000) & 0xFFFF0000;
}
-static inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
+static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
{
/* No error here: 6 bits are used */
return op1 << (op2 & 0x3F);
}
-static inline int32_t _do_esrws (int32_t op1, uint32_t op2)
+static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
{
/* No error here: 6 bits are used */
return op1 >> (op2 & 0x3F);
}
-static inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
+static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
{
/* No error here: 6 bits are used */
return op1 >> (op2 & 0x3F);
}
-static inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
+static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
{
return op2 - op1;
}
@@ -1559,7 +1986,7 @@ DO_SPE_OP2(srwu);
DO_SPE_OP2(subfw);
/* evsel is a little bit more complicated... */
-static inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
+static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
{
if (n)
return op1;
@@ -1582,31 +2009,31 @@ void do_ev##name (void) \
_do_e##name(T0_64, T1_64)); \
}
-static inline uint32_t _do_evcmp_merge (int t0, int t1)
+static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
{
return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
}
-static inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
+static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
{
return op1 == op2 ? 1 : 0;
}
-static inline int _do_ecmpgts (int32_t op1, int32_t op2)
+static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
{
return op1 > op2 ? 1 : 0;
}
-static inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
+static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
{
return op1 > op2 ? 1 : 0;
}
-static inline int _do_ecmplts (int32_t op1, int32_t op2)
+static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
{
return op1 < op2 ? 1 : 0;
}
-static inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
+static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
{
return op1 < op2 ? 1 : 0;
}
@@ -1623,7 +2050,7 @@ DO_SPE_CMP(cmplts);
DO_SPE_CMP(cmpltu);
/* Single precision floating-point conversions from/to integer */
-static inline uint32_t _do_efscfsi (int32_t val)
+static always_inline uint32_t _do_efscfsi (int32_t val)
{
union {
uint32_t u;
@@ -1635,7 +2062,7 @@ static inline uint32_t _do_efscfsi (int32_t val)
return u.u;
}
-static inline uint32_t _do_efscfui (uint32_t val)
+static always_inline uint32_t _do_efscfui (uint32_t val)
{
union {
uint32_t u;
@@ -1647,7 +2074,7 @@ static inline uint32_t _do_efscfui (uint32_t val)
return u.u;
}
-static inline int32_t _do_efsctsi (uint32_t val)
+static always_inline int32_t _do_efsctsi (uint32_t val)
{
union {
int32_t u;
@@ -1662,7 +2089,7 @@ static inline int32_t _do_efsctsi (uint32_t val)
return float32_to_int32(u.f, &env->spe_status);
}
-static inline uint32_t _do_efsctui (uint32_t val)
+static always_inline uint32_t _do_efsctui (uint32_t val)
{
union {
int32_t u;
@@ -1677,7 +2104,7 @@ static inline uint32_t _do_efsctui (uint32_t val)
return float32_to_uint32(u.f, &env->spe_status);
}
-static inline int32_t _do_efsctsiz (uint32_t val)
+static always_inline int32_t _do_efsctsiz (uint32_t val)
{
union {
int32_t u;
@@ -1692,7 +2119,7 @@ static inline int32_t _do_efsctsiz (uint32_t val)
return float32_to_int32_round_to_zero(u.f, &env->spe_status);
}
-static inline uint32_t _do_efsctuiz (uint32_t val)
+static always_inline uint32_t _do_efsctuiz (uint32_t val)
{
union {
int32_t u;
@@ -1738,7 +2165,7 @@ void do_efsctuiz (void)
}
/* Single precision floating-point conversion to/from fractional */
-static inline uint32_t _do_efscfsf (uint32_t val)
+static always_inline uint32_t _do_efscfsf (uint32_t val)
{
union {
uint32_t u;
@@ -1753,7 +2180,7 @@ static inline uint32_t _do_efscfsf (uint32_t val)
return u.u;
}
-static inline uint32_t _do_efscfuf (uint32_t val)
+static always_inline uint32_t _do_efscfuf (uint32_t val)
{
union {
uint32_t u;
@@ -1768,7 +2195,7 @@ static inline uint32_t _do_efscfuf (uint32_t val)
return u.u;
}
-static inline int32_t _do_efsctsf (uint32_t val)
+static always_inline int32_t _do_efsctsf (uint32_t val)
{
union {
int32_t u;
@@ -1786,7 +2213,7 @@ static inline int32_t _do_efsctsf (uint32_t val)
return float32_to_int32(u.f, &env->spe_status);
}
-static inline uint32_t _do_efsctuf (uint32_t val)
+static always_inline uint32_t _do_efsctuf (uint32_t val)
{
union {
int32_t u;
@@ -1804,7 +2231,7 @@ static inline uint32_t _do_efsctuf (uint32_t val)
return float32_to_uint32(u.f, &env->spe_status);
}
-static inline int32_t _do_efsctsfz (uint32_t val)
+static always_inline int32_t _do_efsctsfz (uint32_t val)
{
union {
int32_t u;
@@ -1822,7 +2249,7 @@ static inline int32_t _do_efsctsfz (uint32_t val)
return float32_to_int32_round_to_zero(u.f, &env->spe_status);
}
-static inline uint32_t _do_efsctufz (uint32_t val)
+static always_inline uint32_t _do_efsctufz (uint32_t val)
{
union {
int32_t u;
@@ -1871,19 +2298,19 @@ void do_efsctufz (void)
}
/* Double precision floating point helpers */
-static inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
+static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return _do_efdtstlt(op1, op2);
}
-static inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
+static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return _do_efdtstgt(op1, op2);
}
-static inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
+static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return _do_efdtsteq(op1, op2);
@@ -1905,7 +2332,7 @@ void do_efdcmpeq (void)
}
/* Double precision floating-point conversion to/from integer */
-static inline uint64_t _do_efdcfsi (int64_t val)
+static always_inline uint64_t _do_efdcfsi (int64_t val)
{
union {
uint64_t u;
@@ -1917,7 +2344,7 @@ static inline uint64_t _do_efdcfsi (int64_t val)
return u.u;
}
-static inline uint64_t _do_efdcfui (uint64_t val)
+static always_inline uint64_t _do_efdcfui (uint64_t val)
{
union {
uint64_t u;
@@ -1929,7 +2356,7 @@ static inline uint64_t _do_efdcfui (uint64_t val)
return u.u;
}
-static inline int64_t _do_efdctsi (uint64_t val)
+static always_inline int64_t _do_efdctsi (uint64_t val)
{
union {
int64_t u;
@@ -1944,7 +2371,7 @@ static inline int64_t _do_efdctsi (uint64_t val)
return float64_to_int64(u.f, &env->spe_status);
}
-static inline uint64_t _do_efdctui (uint64_t val)
+static always_inline uint64_t _do_efdctui (uint64_t val)
{
union {
int64_t u;
@@ -1959,7 +2386,7 @@ static inline uint64_t _do_efdctui (uint64_t val)
return float64_to_uint64(u.f, &env->spe_status);
}
-static inline int64_t _do_efdctsiz (uint64_t val)
+static always_inline int64_t _do_efdctsiz (uint64_t val)
{
union {
int64_t u;
@@ -1974,7 +2401,7 @@ static inline int64_t _do_efdctsiz (uint64_t val)
return float64_to_int64_round_to_zero(u.f, &env->spe_status);
}
-static inline uint64_t _do_efdctuiz (uint64_t val)
+static always_inline uint64_t _do_efdctuiz (uint64_t val)
{
union {
int64_t u;
@@ -2020,7 +2447,7 @@ void do_efdctuiz (void)
}
/* Double precision floating-point conversion to/from fractional */
-static inline uint64_t _do_efdcfsf (int64_t val)
+static always_inline uint64_t _do_efdcfsf (int64_t val)
{
union {
uint64_t u;
@@ -2035,7 +2462,7 @@ static inline uint64_t _do_efdcfsf (int64_t val)
return u.u;
}
-static inline uint64_t _do_efdcfuf (uint64_t val)
+static always_inline uint64_t _do_efdcfuf (uint64_t val)
{
union {
uint64_t u;
@@ -2050,7 +2477,7 @@ static inline uint64_t _do_efdcfuf (uint64_t val)
return u.u;
}
-static inline int64_t _do_efdctsf (uint64_t val)
+static always_inline int64_t _do_efdctsf (uint64_t val)
{
union {
int64_t u;
@@ -2068,7 +2495,7 @@ static inline int64_t _do_efdctsf (uint64_t val)
return float64_to_int32(u.f, &env->spe_status);
}
-static inline uint64_t _do_efdctuf (uint64_t val)
+static always_inline uint64_t _do_efdctuf (uint64_t val)
{
union {
int64_t u;
@@ -2086,7 +2513,7 @@ static inline uint64_t _do_efdctuf (uint64_t val)
return float64_to_uint32(u.f, &env->spe_status);
}
-static inline int64_t _do_efdctsfz (uint64_t val)
+static always_inline int64_t _do_efdctsfz (uint64_t val)
{
union {
int64_t u;
@@ -2104,7 +2531,7 @@ static inline int64_t _do_efdctsfz (uint64_t val)
return float64_to_int32_round_to_zero(u.f, &env->spe_status);
}
-static inline uint64_t _do_efdctufz (uint64_t val)
+static always_inline uint64_t _do_efdctufz (uint64_t val)
{
union {
int64_t u;
@@ -2153,7 +2580,7 @@ void do_efdctufz (void)
}
/* Floating point conversion between single and double precision */
-static inline uint32_t _do_efscfd (uint64_t val)
+static always_inline uint32_t _do_efscfd (uint64_t val)
{
union {
uint64_t u;
@@ -2170,7 +2597,7 @@ static inline uint32_t _do_efscfd (uint64_t val)
return u2.u;
}
-static inline uint64_t _do_efdcfs (uint32_t val)
+static always_inline uint64_t _do_efdcfs (uint32_t val)
{
union {
uint64_t u;
@@ -2214,19 +2641,19 @@ DO_SPE_OP2(fsmul);
DO_SPE_OP2(fsdiv);
/* Single-precision floating-point comparisons */
-static inline int _do_efscmplt (uint32_t op1, uint32_t op2)
+static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return _do_efststlt(op1, op2);
}
-static inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
+static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return _do_efststgt(op1, op2);
}
-static inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
+static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return _do_efststeq(op1, op2);
@@ -2282,14 +2709,17 @@ DO_SPE_OP1(fsctuiz);
DO_SPE_OP1(fsctsf);
/* evfsctuf */
DO_SPE_OP1(fsctuf);
-#endif /* defined(TARGET_PPCEMB) */
/*****************************************************************************/
/* Softmmu support */
#if !defined (CONFIG_USER_ONLY)
#define MMUSUFFIX _mmu
-#define GETPC() (__builtin_return_address(0))
+#ifdef __s390__
+# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
+#else
+# define GETPC() (__builtin_return_address(0))
+#endif
#define SHIFT 0
#include "softmmu_template.h"
@@ -2307,22 +2737,22 @@ DO_SPE_OP1(fsctuf);
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
+void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
- target_phys_addr_t pc;
+ unsigned long pc;
int ret;
/* XXX: hack to restore env in all cases, even if not called from
generated code */
saved_env = env;
env = cpu_single_env;
- ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
+ ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */
- pc = (target_phys_addr_t)(unsigned long)retaddr;
+ pc = (unsigned long)retaddr;
tb = tb_find_pc(pc);
if (likely(tb)) {
/* the PC is inside the translated code. It means that we have
@@ -2353,9 +2783,9 @@ void do_load_6xx_tlb (int is_code)
way = (env->spr[SPR_SRR1] >> 17) & 1;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
- __func__, (unsigned long)T0, (unsigned long)EPN,
- (unsigned long)CMP, (unsigned long)RPN, way);
+ fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
+ " PTE1 " ADDRX " way %d\n",
+ __func__, T0, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
@@ -2374,9 +2804,9 @@ void do_load_74xx_tlb (int is_code)
way = env->spr[SPR_TLBMISS] & 0x3;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
- __func__, (unsigned long)T0, (unsigned long)EPN,
- (unsigned long)CMP, (unsigned long)RPN, way);
+ fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
+ " PTE1 " ADDRX " way %d\n",
+ __func__, T0, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
@@ -2384,12 +2814,12 @@ void do_load_74xx_tlb (int is_code)
way, is_code, CMP, RPN);
}
-static target_ulong booke_tlb_to_page_size (int size)
+static always_inline target_ulong booke_tlb_to_page_size (int size)
{
return 1024 << (2 * size);
}
-static int booke_page_size_to_tlb (target_ulong page_size)
+static always_inline int booke_page_size_to_tlb (target_ulong page_size)
{
int size;
@@ -2490,7 +2920,7 @@ void do_4xx_tlbwe_hi (void)
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
+ fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
}
#endif
T0 &= 0x3F;
@@ -2559,7 +2989,7 @@ void do_4xx_tlbwe_lo (void)
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
+ fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
}
#endif
T0 &= 0x3F;
@@ -2592,7 +3022,7 @@ void do_440_tlbwe (int word)
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s word %d T0 " REGX " T1 " REGX "\n",
+ fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
__func__, word, T0, T1);
}
#endif