diff options
Diffstat (limited to 'target-ppc/exec.h')
-rw-r--r-- | target-ppc/exec.h | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/target-ppc/exec.h b/target-ppc/exec.h index 8a5425827..76fdb0b1d 100644 --- a/target-ppc/exec.h +++ b/target-ppc/exec.h @@ -37,13 +37,15 @@ register struct CPUPPCState *env asm(AREG0); #define T0 (env->t0) #define T1 (env->t1) #define T2 (env->t2) +#define TDX "%016" PRIx64 #else register unsigned long T0 asm(AREG1); register unsigned long T1 asm(AREG2); register unsigned long T2 asm(AREG3); +#define TDX "%016lx" #endif -/* We may, sometime, need 64 bits registers on 32 bits target */ -#if TARGET_GPR_BITS > HOST_LONG_BITS +/* We may, sometime, need 64 bits registers on 32 bits targets */ +#if (HOST_LONG_BITS == 32) /* no registers can be used */ #define T0_64 (env->t0) #define T1_64 (env->t1) @@ -54,9 +56,9 @@ register unsigned long T2 asm(AREG3); #define T2_64 T2 #endif /* Provision for Altivec */ -#define T0_avr (env->t0_avr) -#define T1_avr (env->t1_avr) -#define T2_avr (env->t2_avr) +#define AVR0 (env->avr0) +#define AVR1 (env->avr1) +#define AVR2 (env->avr2) #define FT0 (env->ft0) #define FT1 (env->ft1) @@ -68,23 +70,23 @@ register unsigned long T2 asm(AREG3); # define RETURN() __asm__ __volatile__("" : : : "memory"); #endif -static inline target_ulong rotl8 (target_ulong i, int n) +static always_inline target_ulong rotl8 (target_ulong i, int n) { return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n))); } -static inline target_ulong rotl16 (target_ulong i, int n) +static always_inline target_ulong rotl16 (target_ulong i, int n) { return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n))); } -static inline target_ulong rotl32 (target_ulong i, int n) +static always_inline target_ulong rotl32 (target_ulong i, int n) { return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n))); } #if defined(TARGET_PPC64) -static inline target_ulong rotl64 (target_ulong i, int n) +static always_inline target_ulong rotl64 (target_ulong i, int n) { return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n))); } @@ -98,27 +100,27 @@ void do_raise_exception_err (uint32_t exception, int error_code); void do_raise_exception (uint32_t exception); int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr, - int rw, int access_type, int check_BATs); + int rw, int access_type); void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, target_ulong pte0, target_ulong pte1); -static inline void env_to_regs (void) +static always_inline void env_to_regs (void) { } -static inline void regs_to_env (void) +static always_inline void regs_to_env (void) { } int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, - int is_user, int is_softmmu); + int mmu_idx, int is_softmmu); -static inline int cpu_halted (CPUState *env) +static always_inline int cpu_halted (CPUState *env) { if (!env->halted) return 0; - if (env->msr[MSR_EE] && (env->interrupt_request & CPU_INTERRUPT_HARD)) { + if (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)) { env->halted = 0; return 0; } |