diff options
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 93 |
1 files changed, 48 insertions, 45 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index fdb05ccfd..3ec867a72 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -134,33 +134,51 @@ typedef struct mips_def_t mips_def_t; #define MIPS_TC_MAX 5 #define MIPS_DSP_ACC 4 +typedef struct TCState TCState; +struct TCState { + target_ulong gpr[32]; + target_ulong PC; + target_ulong HI[MIPS_DSP_ACC]; + target_ulong LO[MIPS_DSP_ACC]; + target_ulong ACX[MIPS_DSP_ACC]; + target_ulong DSPControl; + int32_t CP0_TCStatus; +#define CP0TCSt_TCU3 31 +#define CP0TCSt_TCU2 30 +#define CP0TCSt_TCU1 29 +#define CP0TCSt_TCU0 28 +#define CP0TCSt_TMX 27 +#define CP0TCSt_RNST 23 +#define CP0TCSt_TDS 21 +#define CP0TCSt_DT 20 +#define CP0TCSt_DA 15 +#define CP0TCSt_A 13 +#define CP0TCSt_TKSU 11 +#define CP0TCSt_IXMT 10 +#define CP0TCSt_TASID 0 + int32_t CP0_TCBind; +#define CP0TCBd_CurTC 21 +#define CP0TCBd_TBE 17 +#define CP0TCBd_CurVPE 0 + target_ulong CP0_TCHalt; + target_ulong CP0_TCContext; + target_ulong CP0_TCSchedule; + target_ulong CP0_TCScheFBack; + int32_t CP0_Debug_tcstatus; +}; + typedef struct CPUMIPSState CPUMIPSState; struct CPUMIPSState { - /* General integer registers */ - target_ulong gpr[MIPS_SHADOW_SET_MAX][32]; - /* Special registers */ - target_ulong PC[MIPS_TC_MAX]; - /* temporary hack for FP globals */ -#ifndef USE_HOST_FLOAT_REGS - fpr_t ft0; - fpr_t ft1; - fpr_t ft2; -#endif - target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC]; - target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC]; - target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC]; - target_ulong DSPControl[MIPS_TC_MAX]; + TCState active_tc; CPUMIPSMVPContext *mvp; CPUMIPSTLBContext *tlb; CPUMIPSFPUContext *fpu; uint32_t current_tc; - target_ulong *current_tc_gprs; - target_ulong *current_tc_hi; uint32_t SEGBITS; - target_ulong SEGMask; uint32_t PABITS; + target_ulong SEGMask; target_ulong PAMask; int32_t CP0_Index; @@ -206,28 +224,6 @@ struct CPUMIPSState { #define CP0VPEOpt_DWX1 1 #define CP0VPEOpt_DWX0 0 target_ulong CP0_EntryLo0; - int32_t CP0_TCStatus[MIPS_TC_MAX]; -#define CP0TCSt_TCU3 31 -#define CP0TCSt_TCU2 30 -#define CP0TCSt_TCU1 29 -#define CP0TCSt_TCU0 28 -#define CP0TCSt_TMX 27 -#define CP0TCSt_RNST 23 -#define CP0TCSt_TDS 21 -#define CP0TCSt_DT 20 -#define CP0TCSt_DA 15 -#define CP0TCSt_A 13 -#define CP0TCSt_TKSU 11 -#define CP0TCSt_IXMT 10 -#define CP0TCSt_TASID 0 - int32_t CP0_TCBind[MIPS_TC_MAX]; -#define CP0TCBd_CurTC 21 -#define CP0TCBd_TBE 17 -#define CP0TCBd_CurVPE 0 - target_ulong CP0_TCHalt[MIPS_TC_MAX]; - target_ulong CP0_TCContext[MIPS_TC_MAX]; - target_ulong CP0_TCSchedule[MIPS_TC_MAX]; - target_ulong CP0_TCScheFBack[MIPS_TC_MAX]; target_ulong CP0_EntryLo1; target_ulong CP0_Context; int32_t CP0_PageMask; @@ -398,7 +394,6 @@ struct CPUMIPSState { #define CP0DB_DDBL 2 #define CP0DB_DBp 1 #define CP0DB_DSS 0 - int32_t CP0_Debug_tcstatus[MIPS_TC_MAX]; target_ulong CP0_DEPC; int32_t CP0_Performance0; int32_t CP0_TagLo; @@ -407,10 +402,10 @@ struct CPUMIPSState { int32_t CP0_DataHi; target_ulong CP0_ErrorEPC; int32_t CP0_DESAVE; + /* We waste some space so we can handle shadow registers like TCs. */ + TCState tcs[MIPS_SHADOW_SET_MAX]; /* Qemu */ - int interrupt_request; int error_code; - int user_mode_only; /* user mode only simulation */ uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x01FF @@ -486,6 +481,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list +#define CPU_SAVE_VERSION 3 + /* MMU modes definitions. We carefully match the indices with our hflags layout. */ #define MMU_MODE0_SUFFIX _kernel @@ -501,9 +498,9 @@ static inline int cpu_mmu_index (CPUState *env) static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) { if (newsp) - env->gpr[env->current_tc][29] = newsp; - env->gpr[env->current_tc][7] = 0; - env->gpr[env->current_tc][2] = 0; + env->active_tc.gpr[29] = newsp; + env->active_tc.gpr[7] = 0; + env->active_tc.gpr[2] = 0; } #endif @@ -569,4 +566,10 @@ CPUMIPSState *cpu_mips_init(const char *cpu_model); uint32_t cpu_mips_get_clock (void); int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); +#define CPU_PC_FROM_TB(env, tb) do { \ + env->active_tc.PC = tb->pc; \ + env->hflags &= ~MIPS_HFLAG_BMASK; \ + env->hflags |= tb->flags & MIPS_HFLAG_BMASK; \ + } while (0) + #endif /* !defined (__MIPS_CPU_H__) */ |