diff options
Diffstat (limited to 'target-microblaze/op_helper.c')
| -rw-r--r-- | target-microblaze/op_helper.c | 115 |
1 files changed, 52 insertions, 63 deletions
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index 3b1f07243..c9789f44c 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -20,7 +20,6 @@ #include <assert.h> #include "cpu.h" -#include "dyngen-exec.h" #include "helper.h" #include "host-utils.h" @@ -42,17 +41,12 @@ /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { TranslationBlock *tb; - CPUMBState *saved_env; int ret; - saved_env = env; - env = env1; - ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { @@ -66,7 +60,6 @@ void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx, } cpu_loop_exit(env); } - env = saved_env; } #endif @@ -105,13 +98,13 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl) return 0xdead0000 | id; } -void helper_raise_exception(uint32_t index) +void helper_raise_exception(CPUMBState *env, uint32_t index) { env->exception_index = index; cpu_loop_exit(env); } -void helper_debug(void) +void helper_debug(CPUMBState *env) { int i; @@ -176,7 +169,7 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) return ncf; } -static inline int div_prepare(uint32_t a, uint32_t b) +static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { if (b == 0) { env->sregs[SR_MSR] |= MSR_DZ; @@ -184,7 +177,7 @@ static inline int div_prepare(uint32_t a, uint32_t b) if ((env->sregs[SR_MSR] & MSR_EE) && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) { env->sregs[SR_ESR] = ESR_EC_DIVZERO; - helper_raise_exception(EXCP_HW_EXCP); + helper_raise_exception(env, EXCP_HW_EXCP); } return 0; } @@ -192,28 +185,30 @@ static inline int div_prepare(uint32_t a, uint32_t b) return 1; } -uint32_t helper_divs(uint32_t a, uint32_t b) +uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(a, b)) + if (!div_prepare(env, a, b)) { return 0; + } return (int32_t)a / (int32_t)b; } -uint32_t helper_divu(uint32_t a, uint32_t b) +uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(a, b)) + if (!div_prepare(env, a, b)) { return 0; + } return a / b; } /* raise FPU exception. */ -static void raise_fpu_exception(void) +static void raise_fpu_exception(CPUMBState *env) { env->sregs[SR_ESR] = ESR_EC_FPU; - helper_raise_exception(EXCP_HW_EXCP); + helper_raise_exception(env, EXCP_HW_EXCP); } -static void update_fpu_flags(int flags) +static void update_fpu_flags(CPUMBState *env, int flags) { int raise = 0; @@ -236,11 +231,11 @@ static void update_fpu_flags(int flags) if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) && (env->sregs[SR_MSR] & MSR_EE)) { - raise_fpu_exception(); + raise_fpu_exception(env); } } -uint32_t helper_fadd(uint32_t a, uint32_t b) +uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fd, fa, fb; int flags; @@ -251,11 +246,11 @@ uint32_t helper_fadd(uint32_t a, uint32_t b) fd.f = float32_add(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags); + update_fpu_flags(env, flags); return fd.l; } -uint32_t helper_frsub(uint32_t a, uint32_t b) +uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fd, fa, fb; int flags; @@ -265,11 +260,11 @@ uint32_t helper_frsub(uint32_t a, uint32_t b) fb.l = b; fd.f = float32_sub(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags); + update_fpu_flags(env, flags); return fd.l; } -uint32_t helper_fmul(uint32_t a, uint32_t b) +uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fd, fa, fb; int flags; @@ -279,12 +274,12 @@ uint32_t helper_fmul(uint32_t a, uint32_t b) fb.l = b; fd.f = float32_mul(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags); + update_fpu_flags(env, flags); return fd.l; } -uint32_t helper_fdiv(uint32_t a, uint32_t b) +uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fd, fa, fb; int flags; @@ -294,12 +289,12 @@ uint32_t helper_fdiv(uint32_t a, uint32_t b) fb.l = b; fd.f = float32_div(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags); + update_fpu_flags(env, flags); return fd.l; } -uint32_t helper_fcmp_un(uint32_t a, uint32_t b) +uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fa, fb; uint32_t r = 0; @@ -308,7 +303,7 @@ uint32_t helper_fcmp_un(uint32_t a, uint32_t b) fb.l = b; if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) { - update_fpu_flags(float_flag_invalid); + update_fpu_flags(env, float_flag_invalid); r = 1; } @@ -319,7 +314,7 @@ uint32_t helper_fcmp_un(uint32_t a, uint32_t b) return r; } -uint32_t helper_fcmp_lt(uint32_t a, uint32_t b) +uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fa, fb; int r; @@ -330,12 +325,12 @@ uint32_t helper_fcmp_lt(uint32_t a, uint32_t b) fb.l = b; r = float32_lt(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid); return r; } -uint32_t helper_fcmp_eq(uint32_t a, uint32_t b) +uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fa, fb; int flags; @@ -346,12 +341,12 @@ uint32_t helper_fcmp_eq(uint32_t a, uint32_t b) fb.l = b; r = float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid); return r; } -uint32_t helper_fcmp_le(uint32_t a, uint32_t b) +uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fa, fb; int flags; @@ -362,13 +357,13 @@ uint32_t helper_fcmp_le(uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = float32_le(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid); return r; } -uint32_t helper_fcmp_gt(uint32_t a, uint32_t b) +uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fa, fb; int flags, r; @@ -378,11 +373,11 @@ uint32_t helper_fcmp_gt(uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = float32_lt(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid); return r; } -uint32_t helper_fcmp_ne(uint32_t a, uint32_t b) +uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fa, fb; int flags, r; @@ -392,12 +387,12 @@ uint32_t helper_fcmp_ne(uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid); return r; } -uint32_t helper_fcmp_ge(uint32_t a, uint32_t b) +uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) { CPU_FloatU fa, fb; int flags, r; @@ -407,12 +402,12 @@ uint32_t helper_fcmp_ge(uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = !float32_lt(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid); return r; } -uint32_t helper_flt(uint32_t a) +uint32_t helper_flt(CPUMBState *env, uint32_t a) { CPU_FloatU fd, fa; @@ -421,7 +416,7 @@ uint32_t helper_flt(uint32_t a) return fd.l; } -uint32_t helper_fint(uint32_t a) +uint32_t helper_fint(CPUMBState *env, uint32_t a) { CPU_FloatU fa; uint32_t r; @@ -431,12 +426,12 @@ uint32_t helper_fint(uint32_t a) fa.l = a; r = float32_to_int32(fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags); + update_fpu_flags(env, flags); return r; } -uint32_t helper_fsqrt(uint32_t a) +uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) { CPU_FloatU fd, fa; int flags; @@ -445,7 +440,7 @@ uint32_t helper_fsqrt(uint32_t a) fa.l = a; fd.l = float32_sqrt(fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(flags); + update_fpu_flags(env, flags); return fd.l; } @@ -463,7 +458,8 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b) return 0; } -void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask) +void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr, + uint32_t mask) { if (addr & mask) { qemu_log_mask(CPU_LOG_INT, @@ -478,45 +474,39 @@ void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask) if (!(env->sregs[SR_MSR] & MSR_EE)) { return; } - helper_raise_exception(EXCP_HW_EXCP); + helper_raise_exception(env, EXCP_HW_EXCP); } } -void helper_stackprot(uint32_t addr) +void helper_stackprot(CPUMBState *env, uint32_t addr) { if (addr < env->slr || addr > env->shr) { qemu_log("Stack protector violation at %x %x %x\n", addr, env->slr, env->shr); env->sregs[SR_EAR] = addr; env->sregs[SR_ESR] = ESR_EC_STACKPROT; - helper_raise_exception(EXCP_HW_EXCP); + helper_raise_exception(env, EXCP_HW_EXCP); } } #if !defined(CONFIG_USER_ONLY) /* Writes/reads to the MMU's special regs end up here. */ -uint32_t helper_mmu_read(uint32_t rn) +uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn) { return mmu_read(env, rn); } -void helper_mmu_write(uint32_t rn, uint32_t v) +void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) { mmu_write(env, rn, v); } -void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr, +void cpu_unassigned_access(CPUMBState *env, target_phys_addr_t addr, int is_write, int is_exec, int is_asi, int size) { - CPUMBState *saved_env; - - saved_env = env; - env = env1; - qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n", addr, is_write, is_exec); if (!(env->sregs[SR_MSR] & MSR_EE)) { - env = saved_env; return; } @@ -524,14 +514,13 @@ void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr, if (is_exec) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { env->sregs[SR_ESR] = ESR_EC_INSN_BUS; - helper_raise_exception(EXCP_HW_EXCP); + helper_raise_exception(env, EXCP_HW_EXCP); } } else { if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { env->sregs[SR_ESR] = ESR_EC_DATA_BUS; - helper_raise_exception(EXCP_HW_EXCP); + helper_raise_exception(env, EXCP_HW_EXCP); } } - env = saved_env; } #endif |