diff options
Diffstat (limited to 'hw/omap.c')
| -rw-r--r-- | hw/omap.c | 3869 |
1 files changed, 3356 insertions, 513 deletions
@@ -18,100 +18,130 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#include "vl.h" -#include "arm_pic.h" +#include "hw.h" +#include "arm-misc.h" +#include "omap.h" +#include "sysemu.h" +#include "qemu-timer.h" +/* We use pc-style serial ports. */ +#include "pc.h" /* Should signal the TCMI */ +uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr) +{ + uint8_t ret; + + OMAP_8B_REG(addr); + cpu_physical_memory_read(addr, (void *) &ret, 1); + return ret; +} + +void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + uint8_t val8 = value; + + OMAP_8B_REG(addr); + cpu_physical_memory_write(addr, (void *) &val8, 1); +} + uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr) { + uint16_t ret; + OMAP_16B_REG(addr); - return 0; + cpu_physical_memory_read(addr, (void *) &ret, 2); + return ret; } void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, uint32_t value) { + uint16_t val16 = value; + OMAP_16B_REG(addr); + cpu_physical_memory_write(addr, (void *) &val16, 2); } uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr) { + uint32_t ret; + OMAP_32B_REG(addr); - return 0; + cpu_physical_memory_read(addr, (void *) &ret, 4); + return ret; } void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, uint32_t value) { OMAP_32B_REG(addr); + cpu_physical_memory_write(addr, (void *) &value, 4); } /* Interrupt Handlers */ +struct omap_intr_handler_bank_s { + uint32_t irqs; + uint32_t inputs; + uint32_t mask; + uint32_t fiq; + uint32_t sens_edge; + unsigned char priority[32]; +}; + struct omap_intr_handler_s { qemu_irq *pins; - qemu_irq *parent_pic; + qemu_irq parent_intr[2]; target_phys_addr_t base; + unsigned char nbanks; /* state */ - uint32_t irqs; - uint32_t mask; - uint32_t sens_edge; - uint32_t fiq; - int priority[32]; - uint32_t new_irq_agr; - uint32_t new_fiq_agr; - int sir_irq; - int sir_fiq; - int stats[32]; + uint32_t new_agr[2]; + int sir_intr[2]; + struct omap_intr_handler_bank_s banks[]; }; -static void omap_inth_update(struct omap_intr_handler_s *s) +static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) { - uint32_t irq = s->irqs & ~s->mask & ~s->fiq; - uint32_t fiq = s->irqs & ~s->mask & s->fiq; - - if (s->new_irq_agr || !irq) { - qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ], irq); - if (irq) - s->new_irq_agr = 0; - } - - if (s->new_fiq_agr || !irq) { - qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ], fiq); - if (fiq) - s->new_fiq_agr = 0; + int i, j, sir_intr, p_intr, p, f; + uint32_t level; + sir_intr = 0; + p_intr = 255; + + /* Find the interrupt line with the highest dynamic priority. + * Note: 0 denotes the hightest priority. + * If all interrupts have the same priority, the default order is IRQ_N, + * IRQ_N-1,...,IRQ_0. */ + for (j = 0; j < s->nbanks; ++j) { + level = s->banks[j].irqs & ~s->banks[j].mask & + (is_fiq ? s->banks[j].fiq : ~s->banks[j].fiq); + for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, + level >>= f) { + p = s->banks[j].priority[i]; + if (p <= p_intr) { + p_intr = p; + sir_intr = 32 * j + i; + } + f = ffs(level >> 1); + } } + s->sir_intr[is_fiq] = sir_intr; } -static void omap_inth_sir_update(struct omap_intr_handler_s *s) +static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) { - int i, intr_irq, intr_fiq, p_irq, p_fiq, p, f; - uint32_t level = s->irqs & ~s->mask; + int i; + uint32_t has_intr = 0; - intr_irq = 0; - intr_fiq = 0; - p_irq = -1; - p_fiq = -1; - /* Find the interrupt line with the highest dynamic priority */ - for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, level >>= f) { - p = s->priority[i]; - if (s->fiq & (1 << i)) { - if (p > p_fiq) { - p_fiq = p; - intr_fiq = i; - } - } else { - if (p > p_irq) { - p_irq = p; - intr_irq = i; - } - } + for (i = 0; i < s->nbanks; ++i) + has_intr |= s->banks[i].irqs & ~s->banks[i].mask & + (is_fiq ? s->banks[i].fiq : ~s->banks[i].fiq); - f = ffs(level >> 1); + if (s->new_agr[is_fiq] && has_intr) { + s->new_agr[is_fiq] = 0; + omap_inth_sir_update(s, is_fiq); + qemu_set_irq(s->parent_intr[is_fiq], 1); } - - s->sir_irq = intr_irq; - s->sir_fiq = intr_fiq; } #define INT_FALLING_EDGE 0 @@ -122,19 +152,24 @@ static void omap_set_intr(void *opaque, int irq, int req) struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; uint32_t rise; + struct omap_intr_handler_bank_s *bank = &ih->banks[irq >> 5]; + int n = irq & 31; + if (req) { - rise = ~ih->irqs & (1 << irq); - ih->irqs |= rise; - ih->stats[irq] += !!rise; + rise = ~bank->irqs & (1 << n); + if (~bank->sens_edge & (1 << n)) + rise &= ~bank->inputs & (1 << n); + + bank->inputs |= (1 << n); + if (rise) { + bank->irqs |= rise; + omap_inth_update(ih, 0); + omap_inth_update(ih, 1); + } } else { - rise = ih->sens_edge & ih->irqs & (1 << irq); - ih->irqs &= ~rise; - } - - if (rise & ~ih->mask) { - omap_inth_sir_update(ih); - - omap_inth_update(ih); + rise = bank->sens_edge & bank->irqs & (1 << n); + bank->irqs &= ~rise; + bank->inputs &= ~(1 << n); } } @@ -142,33 +177,32 @@ static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; int i, offset = addr - s->base; + int bank_no = offset >> 8; + int line_no; + struct omap_intr_handler_bank_s *bank = &s->banks[bank_no]; + offset &= 0xff; switch (offset) { case 0x00: /* ITR */ - return s->irqs; + return bank->irqs; case 0x04: /* MIR */ - return s->mask; + return bank->mask; case 0x10: /* SIR_IRQ_CODE */ - i = s->sir_irq; - if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { - s->irqs &= ~(1 << i); - omap_inth_sir_update(s); - omap_inth_update(s); - } - return i; - - case 0x14: /* SIR_FIQ_CODE */ - i = s->sir_fiq; - if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { - s->irqs &= ~(1 << i); - omap_inth_sir_update(s); - omap_inth_update(s); - } - return i; + case 0x14: /* SIR_FIQ_CODE */ + if (bank_no != 0) + break; + line_no = s->sir_intr[(offset - 0x10) >> 2]; + bank = &s->banks[line_no >> 5]; + i = line_no & 31; + if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) + bank->irqs &= ~(1 << i); + return line_no; case 0x18: /* CONTROL_REG */ + if (bank_no != 0) + break; return 0; case 0x1c: /* ILR0 */ @@ -204,17 +238,15 @@ static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) case 0x94: /* ILR30 */ case 0x98: /* ILR31 */ i = (offset - 0x1c) >> 2; - return (s->priority[i] << 2) | - (((s->sens_edge >> i) & 1) << 1) | - ((s->fiq >> i) & 1); + return (bank->priority[i] << 2) | + (((bank->sens_edge >> i) & 1) << 1) | + ((bank->fiq >> i) & 1); case 0x9c: /* ISR */ return 0x00000000; - default: - OMAP_BAD_REG(addr); - break; } + OMAP_BAD_REG(addr); return 0; } @@ -223,18 +255,21 @@ static void omap_inth_write(void *opaque, target_phys_addr_t addr, { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; int i, offset = addr - s->base; + int bank_no = offset >> 8; + struct omap_intr_handler_bank_s *bank = &s->banks[bank_no]; + offset &= 0xff; switch (offset) { case 0x00: /* ITR */ - s->irqs &= value; - omap_inth_sir_update(s); - omap_inth_update(s); + /* Important: ignore the clearing if the IRQ is level-triggered and + the input bit is 1 */ + bank->irqs &= value | (bank->inputs & bank->sens_edge); return; case 0x04: /* MIR */ - s->mask = value; - omap_inth_sir_update(s); - omap_inth_update(s); + bank->mask = value; + omap_inth_update(s, 0); + omap_inth_update(s, 1); return; case 0x10: /* SIR_IRQ_CODE */ @@ -243,11 +278,18 @@ static void omap_inth_write(void *opaque, target_phys_addr_t addr, break; case 0x18: /* CONTROL_REG */ - if (value & 2) - s->new_fiq_agr = ~0; - if (value & 1) - s->new_irq_agr = ~0; - omap_inth_update(s); + if (bank_no != 0) + break; + if (value & 2) { + qemu_set_irq(s->parent_intr[1], 0); + s->new_agr[1] = ~0; + omap_inth_update(s, 1); + } + if (value & 1) { + qemu_set_irq(s->parent_intr[0], 0); + s->new_agr[0] = ~0; + omap_inth_update(s, 0); + } return; case 0x1c: /* ILR0 */ @@ -283,24 +325,22 @@ static void omap_inth_write(void *opaque, target_phys_addr_t addr, case 0x94: /* ILR30 */ case 0x98: /* ILR31 */ i = (offset - 0x1c) >> 2; - s->priority[i] = (value >> 2) & 0x1f; - s->sens_edge &= ~(1 << i); - s->sens_edge |= ((value >> 1) & 1) << i; - s->fiq &= ~(1 << i); - s->fiq |= (value & 1) << i; + bank->priority[i] = (value >> 2) & 0x1f; + bank->sens_edge &= ~(1 << i); + bank->sens_edge |= ((value >> 1) & 1) << i; + bank->fiq &= ~(1 << i); + bank->fiq |= (value & 1) << i; return; case 0x9c: /* ISR */ for (i = 0; i < 32; i ++) if (value & (1 << i)) { - omap_set_intr(s, i, 1); + omap_set_intr(s, 32 * bank_no + i, 1); return; } return; - - default: - OMAP_BAD_REG(addr); } + OMAP_BAD_REG(addr); } static CPUReadMemoryFunc *omap_inth_readfn[] = { @@ -315,31 +355,43 @@ static CPUWriteMemoryFunc *omap_inth_writefn[] = { omap_inth_write, }; -static void omap_inth_reset(struct omap_intr_handler_s *s) +void omap_inth_reset(struct omap_intr_handler_s *s) { - s->irqs = 0x00000000; - s->mask = 0xffffffff; - s->sens_edge = 0x00000000; - s->fiq = 0x00000000; - memset(s->priority, 0, sizeof(s->priority)); - s->new_irq_agr = ~0; - s->new_fiq_agr = ~0; - s->sir_irq = 0; - s->sir_fiq = 0; + int i; + + for (i = 0; i < s->nbanks; ++i){ + s->banks[i].irqs = 0x00000000; + s->banks[i].mask = 0xffffffff; + s->banks[i].sens_edge = 0x00000000; + s->banks[i].fiq = 0x00000000; + s->banks[i].inputs = 0x00000000; + memset(s->banks[i].priority, 0, sizeof(s->banks[i].priority)); + } + + s->new_agr[0] = ~0; + s->new_agr[1] = ~0; + s->sir_intr[0] = 0; + s->sir_intr[1] = 0; - omap_inth_update(s); + qemu_set_irq(s->parent_intr[0], 0); + qemu_set_irq(s->parent_intr[1], 0); } struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, - unsigned long size, qemu_irq parent[2], omap_clk clk) + unsigned long size, unsigned char nbanks, + qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) { int iomemtype; struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) - qemu_mallocz(sizeof(struct omap_intr_handler_s)); + qemu_mallocz(sizeof(struct omap_intr_handler_s) + + sizeof(struct omap_intr_handler_bank_s) * nbanks); - s->parent_pic = parent; + s->parent_intr[0] = parent_irq; + s->parent_intr[1] = parent_fiq; s->base = base; - s->pins = qemu_allocate_irqs(omap_set_intr, s, 32); + s->nbanks = nbanks; + s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32); + omap_inth_reset(s); iomemtype = cpu_register_io_memory(0, omap_inth_readfn, @@ -350,38 +402,53 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, } /* OMAP1 DMA module */ -typedef enum { - constant = 0, - post_incremented, - single_index, - double_index, -} omap_dma_addressing_t; - struct omap_dma_channel_s { + /* transfer data */ int burst[2]; int pack[2]; enum omap_dma_port port[2]; target_phys_addr_t addr[2]; omap_dma_addressing_t mode[2]; + uint16_t elements; + uint16_t frames; + int16_t frame_index[2]; + int16_t element_index[2]; int data_type; + + /* transfer type */ + int transparent_copy; + int constant_fill; + uint32_t color; + + /* auto init and linked channel data */ int end_prog; int repeat; int auto_init; - int priority; - int fs; - int sync; - int running; + int link_enabled; + int link_next_ch; + + /* interruption data */ int interrupts; int status; - int signalled; - int post_sync; - int transfer; - uint16_t elements; - uint16_t frames; - uint16_t frame_index; - uint16_t element_index; + + /* state data */ + int active; + int enable; + int sync; + int pending_request; + int waiting_end_prog; uint16_t cpc; + /* sync type */ + int fs; + int bs; + + /* compatibility */ + int omap_3_1_compatible_disable; + + qemu_irq irq; + struct omap_dma_channel_s *sibling; + struct omap_dma_reg_set_s { target_phys_addr_t src, dest; int frame; @@ -391,16 +458,22 @@ struct omap_dma_channel_s { int frames; int elements; } active_set; + + /* unused parameters */ + int priority; + int interleave_disabled; + int type; }; struct omap_dma_s { - qemu_irq *ih; QEMUTimer *tm; struct omap_mpu_state_s *mpu; target_phys_addr_t base; omap_clk clk; int64_t delay; uint32_t drq; + enum omap_dma_model model; + int omap_3_1_mapping_disabled; uint16_t gcr; int run_count; @@ -410,223 +483,302 @@ struct omap_dma_s { struct omap_dma_lcd_channel_s lcd_ch; }; +/* Interrupts */ +#define TIMEOUT_INTR (1 << 0) +#define EVENT_DROP_INTR (1 << 1) +#define HALF_FRAME_INTR (1 << 2) +#define END_FRAME_INTR (1 << 3) +#define LAST_FRAME_INTR (1 << 4) +#define END_BLOCK_INTR (1 << 5) +#define SYNC (1 << 6) + static void omap_dma_interrupts_update(struct omap_dma_s *s) { - /* First three interrupts are shared between two channels each. */ - qemu_set_irq(s->ih[OMAP_INT_DMA_CH0_6], - (s->ch[0].status | s->ch[6].status) & 0x3f); - qemu_set_irq(s->ih[OMAP_INT_DMA_CH1_7], - (s->ch[1].status | s->ch[7].status) & 0x3f); - qemu_set_irq(s->ih[OMAP_INT_DMA_CH2_8], - (s->ch[2].status | s->ch[8].status) & 0x3f); - qemu_set_irq(s->ih[OMAP_INT_DMA_CH3], - (s->ch[3].status) & 0x3f); - qemu_set_irq(s->ih[OMAP_INT_DMA_CH4], - (s->ch[4].status) & 0x3f); - qemu_set_irq(s->ih[OMAP_INT_DMA_CH5], - (s->ch[5].status) & 0x3f); + struct omap_dma_channel_s *ch = s->ch; + int i; + + if (s->omap_3_1_mapping_disabled) { + for (i = 0; i < s->chans; i ++, ch ++) + if (ch->status) + qemu_irq_raise(ch->irq); + } else { + /* First three interrupts are shared between two channels each. */ + for (i = 0; i < 6; i ++, ch ++) { + if (ch->status || (ch->sibling && ch->sibling->status)) + qemu_irq_raise(ch->irq); + } + } } -static void omap_dma_channel_load(struct omap_dma_s *s, int ch) +static void omap_dma_channel_load(struct omap_dma_s *s, + struct omap_dma_channel_s *ch) { - struct omap_dma_reg_set_s *a = &s->ch[ch].active_set; + struct omap_dma_reg_set_s *a = &ch->active_set; int i; + int omap_3_1 = !ch->omap_3_1_compatible_disable; /* * TODO: verify address ranges and alignment * TODO: port endianness */ - a->src = s->ch[ch].addr[0]; - a->dest = s->ch[ch].addr[1]; - a->frames = s->ch[ch].frames; - a->elements = s->ch[ch].elements; + a->src = ch->addr[0]; + a->dest = ch->addr[1]; + a->frames = ch->frames; + a->elements = ch->elements; a->frame = 0; a->element = 0; - if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) { + if (unlikely(!ch->elements || !ch->frames)) { printf("%s: bad DMA request\n", __FUNCTION__); return; } for (i = 0; i < 2; i ++) - switch (s->ch[ch].mode[i]) { + switch (ch->mode[i]) { case constant: a->elem_delta[i] = 0; a->frame_delta[i] = 0; break; case post_incremented: - a->elem_delta[i] = s->ch[ch].data_type; + a->elem_delta[i] = ch->data_type; a->frame_delta[i] = 0; break; case single_index: - a->elem_delta[i] = s->ch[ch].data_type + - s->ch[ch].element_index - 1; - if (s->ch[ch].element_index > 0x7fff) - a->elem_delta[i] -= 0x10000; + a->elem_delta[i] = ch->data_type + + ch->element_index[omap_3_1 ? 0 : i] - 1; a->frame_delta[i] = 0; break; case double_index: - a->elem_delta[i] = s->ch[ch].data_type + - s->ch[ch].element_index - 1; - if (s->ch[ch].element_index > 0x7fff) - a->elem_delta[i] -= 0x10000; - a->frame_delta[i] = s->ch[ch].frame_index - - s->ch[ch].element_index; - if (s->ch[ch].frame_index > 0x7fff) - a->frame_delta[i] -= 0x10000; + a->elem_delta[i] = ch->data_type + + ch->element_index[omap_3_1 ? 0 : i] - 1; + a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] - + ch->element_index[omap_3_1 ? 0 : i]; break; default: break; } } -static inline void omap_dma_request_run(struct omap_dma_s *s, - int channel, int request) +static void omap_dma_activate_channel(struct omap_dma_s *s, + struct omap_dma_channel_s *ch) { -next_channel: - if (request > 0) - for (; channel < 9; channel ++) - if (s->ch[channel].sync == request && s->ch[channel].running) - break; - if (channel >= 9) + if (!ch->active) { + ch->active = 1; + if (ch->sync) + ch->status |= SYNC; + s->run_count ++; + } + + if (s->delay && !qemu_timer_pending(s->tm)) + qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); +} + +static void omap_dma_deactivate_channel(struct omap_dma_s *s, + struct omap_dma_channel_s *ch) +{ + /* Update cpc */ + ch->cpc = ch->active_set.dest & 0xffff; + + if (ch->pending_request && !ch->waiting_end_prog) { + /* Don't deactivate the channel */ + ch->pending_request = 0; return; + } - if (s->ch[channel].transfer) { - if (request > 0) { - s->ch[channel ++].post_sync = request; - goto next_channel; - } - s->ch[channel].status |= 0x02; /* Synchronisation drop */ - omap_dma_interrupts_update(s); + /* Don't deactive the channel if it is synchronized and the DMA request is + active */ + if (ch->sync && (s->drq & (1 << ch->sync))) return; + + if (ch->active) { + ch->active = 0; + ch->status &= ~SYNC; + s->run_count --; } - if (!s->ch[channel].signalled) - s->run_count ++; - s->ch[channel].signalled = 1; + if (!s->run_count) + qemu_del_timer(s->tm); +} - if (request > 0) - s->ch[channel].status |= 0x40; /* External request */ +static void omap_dma_enable_channel(struct omap_dma_s *s, + struct omap_dma_channel_s *ch) +{ + if (!ch->enable) { + ch->enable = 1; + ch->waiting_end_prog = 0; + omap_dma_channel_load(s, ch); + if ((!ch->sync) || (s->drq & (1 << ch->sync))) + omap_dma_activate_channel(s, ch); + } +} - if (s->delay && !qemu_timer_pending(s->tm)) - qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); +static void omap_dma_disable_channel(struct omap_dma_s *s, + struct omap_dma_channel_s *ch) +{ + if (ch->enable) { + ch->enable = 0; + /* Discard any pending request */ + ch->pending_request = 0; + omap_dma_deactivate_channel(s, ch); + } +} - if (request > 0) { - channel ++; - goto next_channel; +static void omap_dma_channel_end_prog(struct omap_dma_s *s, + struct omap_dma_channel_s *ch) +{ + if (ch->waiting_end_prog) { + ch->waiting_end_prog = 0; + if (!ch->sync || ch->pending_request) { + ch->pending_request = 0; + omap_dma_activate_channel(s, ch); + } } } -static inline void omap_dma_request_stop(struct omap_dma_s *s, int channel) +static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) { - if (s->ch[channel].signalled) - s->run_count --; - s->ch[channel].signalled = 0; + s->omap_3_1_mapping_disabled = 0; + s->chans = 9; +} - if (!s->run_count) - qemu_del_timer(s->tm); +static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) +{ + s->omap_3_1_mapping_disabled = 1; + s->chans = 16; +} + +static void omap_dma_process_request(struct omap_dma_s *s, int request) +{ + int channel; + int drop_event = 0; + struct omap_dma_channel_s *ch = s->ch; + + for (channel = 0; channel < s->chans; channel ++, ch ++) { + if (ch->enable && ch->sync == request) { + if (!ch->active) + omap_dma_activate_channel(s, ch); + else if (!ch->pending_request) + ch->pending_request = 1; + else { + /* Request collision */ + /* Second request received while processing other request */ + ch->status |= EVENT_DROP_INTR; + drop_event = 1; + } + } + } + + if (drop_event) + omap_dma_interrupts_update(s); } static void omap_dma_channel_run(struct omap_dma_s *s) { - int ch; + int n = s->chans; uint16_t status; uint8_t value[4]; struct omap_dma_port_if_s *src_p, *dest_p; struct omap_dma_reg_set_s *a; + struct omap_dma_channel_s *ch; - for (ch = 0; ch < 9; ch ++) { - a = &s->ch[ch].active_set; + for (ch = s->ch; n; n --, ch ++) { + if (!ch->active) + continue; - src_p = &s->mpu->port[s->ch[ch].port[0]]; - dest_p = &s->mpu->port[s->ch[ch].port[1]]; - if (s->ch[ch].signalled && (!src_p->addr_valid(s->mpu, a->src) || - !dest_p->addr_valid(s->mpu, a->dest))) { + a = &ch->active_set; + + src_p = &s->mpu->port[ch->port[0]]; + dest_p = &s->mpu->port[ch->port[1]]; + if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) || + (!dest_p->addr_valid(s->mpu, a->dest))) { #if 0 /* Bus time-out */ - if (s->ch[ch].interrupts & 0x01) - s->ch[ch].status |= 0x01; - omap_dma_request_stop(s, ch); + if (ch->interrupts & TIMEOUT_INTR) + ch->status |= TIMEOUT_INTR; + omap_dma_deactivate_channel(s, ch); continue; #endif - printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch); + printf("%s: Bus time-out in DMA%i operation\n", + __FUNCTION__, s->chans - n); } - status = s->ch[ch].status; - while (status == s->ch[ch].status && s->ch[ch].signalled) { + status = ch->status; + while (status == ch->status && ch->active) { /* Transfer a single element */ - s->ch[ch].transfer = 1; - cpu_physical_memory_read(a->src, value, s->ch[ch].data_type); - cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type); - s->ch[ch].transfer = 0; + /* FIXME: check the endianness */ + if (!ch->constant_fill) + cpu_physical_memory_read(a->src, value, ch->data_type); + else + *(uint32_t *) value = ch->color; + + if (!ch->transparent_copy || + *(uint32_t *) value != ch->color) + cpu_physical_memory_write(a->dest, value, ch->data_type); a->src += a->elem_delta[0]; a->dest += a->elem_delta[1]; a->element ++; - /* Check interrupt conditions */ + /* If the channel is element synchronized, deactivate it */ + if (ch->sync && !ch->fs && !ch->bs) + omap_dma_deactivate_channel(s, ch); + + /* If it is the last frame, set the LAST_FRAME interrupt */ + if (a->element == 1 && a->frame == a->frames - 1) + if (ch->interrupts & LAST_FRAME_INTR) + ch->status |= LAST_FRAME_INTR; + + /* If the half of the frame was reached, set the HALF_FRAME + interrupt */ + if (a->element == (a->elements >> 1)) + if (ch->interrupts & HALF_FRAME_INTR) + ch->status |= HALF_FRAME_INTR; + if (a->element == a->elements) { + /* End of Frame */ a->element = 0; a->src += a->frame_delta[0]; a->dest += a->frame_delta[1]; a->frame ++; - if (a->frame == a->frames) { - if (!s->ch[ch].repeat || !s->ch[ch].auto_init) - s->ch[ch].running = 0; - - if (s->ch[ch].auto_init && - (s->ch[ch].repeat || - s->ch[ch].end_prog)) - omap_dma_channel_load(s, ch); + /* If the channel is frame synchronized, deactivate it */ + if (ch->sync && ch->fs) + omap_dma_deactivate_channel(s, ch); - if (s->ch[ch].interrupts & 0x20) - s->ch[ch].status |= 0x20; + /* If the channel is async, update cpc */ + if (!ch->sync) + ch->cpc = a->dest & 0xffff; - if (!s->ch[ch].sync) - omap_dma_request_stop(s, ch); - } + /* Set the END_FRAME interrupt */ + if (ch->interrupts & END_FRAME_INTR) + ch->status |= END_FRAME_INTR; - if (s->ch[ch].interrupts & 0x08) - s->ch[ch].status |= 0x08; - - if (s->ch[ch].sync && s->ch[ch].fs && - !(s->drq & (1 << s->ch[ch].sync))) { - s->ch[ch].status &= ~0x40; - omap_dma_request_stop(s, ch); + if (a->frame == a->frames) { + /* End of Block */ + /* Disable the channel */ + + if (ch->omap_3_1_compatible_disable) { + omap_dma_disable_channel(s, ch); + if (ch->link_enabled) + omap_dma_enable_channel(s, + &s->ch[ch->link_next_ch]); + } else { + if (!ch->auto_init) + omap_dma_disable_channel(s, ch); + else if (ch->repeat || ch->end_prog) + omap_dma_channel_load(s, ch); + else { + ch->waiting_end_prog = 1; + omap_dma_deactivate_channel(s, ch); + } + } + + if (ch->interrupts & END_BLOCK_INTR) + ch->status |= END_BLOCK_INTR; } } - - if (a->element == 1 && a->frame == a->frames - 1) - if (s->ch[ch].interrupts & 0x10) - s->ch[ch].status |= 0x10; - - if (a->element == (a->elements >> 1)) - if (s->ch[ch].interrupts & 0x04) - s->ch[ch].status |= 0x04; - - if (s->ch[ch].sync && !s->ch[ch].fs && - !(s->drq & (1 << s->ch[ch].sync))) { - s->ch[ch].status &= ~0x40; - omap_dma_request_stop(s, ch); - } - - /* - * Process requests made while the element was - * being transferred. - */ - if (s->ch[ch].post_sync) { - omap_dma_request_run(s, 0, s->ch[ch].post_sync); - s->ch[ch].post_sync = 0; - } - -#if 0 - break; -#endif } - - s->ch[ch].cpc = a->dest & 0x0000ffff; } omap_dma_interrupts_update(s); @@ -634,75 +786,174 @@ static void omap_dma_channel_run(struct omap_dma_s *s) qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); } +static void omap_dma_reset(struct omap_dma_s *s) +{ + int i; + + qemu_del_timer(s->tm); + s->gcr = 0x0004; + s->drq = 0x00000000; + s->run_count = 0; + s->lcd_ch.src = emiff; + s->lcd_ch.condition = 0; + s->lcd_ch.interrupts = 0; + s->lcd_ch.dual = 0; + omap_dma_enable_3_1_mapping(s); + for (i = 0; i < s->chans; i ++) { + memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); + memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); + memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); + memset(&s->ch[i].elements, 0, sizeof(s->ch[i].elements)); + memset(&s->ch[i].frames, 0, sizeof(s->ch[i].frames)); + memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); + memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); + memset(&s->ch[i].data_type, 0, sizeof(s->ch[i].data_type)); + memset(&s->ch[i].transparent_copy, 0, + sizeof(s->ch[i].transparent_copy)); + memset(&s->ch[i].constant_fill, 0, sizeof(s->ch[i].constant_fill)); + memset(&s->ch[i].color, 0, sizeof(s->ch[i].color)); + memset(&s->ch[i].end_prog, 0, sizeof(s->ch[i].end_prog)); + memset(&s->ch[i].repeat, 0, sizeof(s->ch[i].repeat)); + memset(&s->ch[i].auto_init, 0, sizeof(s->ch[i].auto_init)); + memset(&s->ch[i].link_enabled, 0, sizeof(s->ch[i].link_enabled)); + memset(&s->ch[i].link_next_ch, 0, sizeof(s->ch[i].link_next_ch)); + s->ch[i].interrupts = 0x0003; + memset(&s->ch[i].status, 0, sizeof(s->ch[i].status)); + memset(&s->ch[i].active, 0, sizeof(s->ch[i].active)); + memset(&s->ch[i].enable, 0, sizeof(s->ch[i].enable)); + memset(&s->ch[i].sync, 0, sizeof(s->ch[i].sync)); + memset(&s->ch[i].pending_request, 0, sizeof(s->ch[i].pending_request)); + memset(&s->ch[i].waiting_end_prog, 0, + sizeof(s->ch[i].waiting_end_prog)); + memset(&s->ch[i].cpc, 0, sizeof(s->ch[i].cpc)); + memset(&s->ch[i].fs, 0, sizeof(s->ch[i].fs)); + memset(&s->ch[i].bs, 0, sizeof(s->ch[i].bs)); + memset(&s->ch[i].omap_3_1_compatible_disable, 0, + sizeof(s->ch[i].omap_3_1_compatible_disable)); + memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); + memset(&s->ch[i].priority, 0, sizeof(s->ch[i].priority)); + memset(&s->ch[i].interleave_disabled, 0, + sizeof(s->ch[i].interleave_disabled)); + memset(&s->ch[i].type, 0, sizeof(s->ch[i].type)); + } +} + static int omap_dma_ch_reg_read(struct omap_dma_s *s, - int ch, int reg, uint16_t *value) { + struct omap_dma_channel_s *ch, int reg, uint16_t *value) +{ switch (reg) { case 0x00: /* SYS_DMA_CSDP_CH0 */ - *value = (s->ch[ch].burst[1] << 14) | - (s->ch[ch].pack[1] << 13) | - (s->ch[ch].port[1] << 9) | - (s->ch[ch].burst[0] << 7) | - (s->ch[ch].pack[0] << 6) | - (s->ch[ch].port[0] << 2) | - (s->ch[ch].data_type >> 1); + *value = (ch->burst[1] << 14) | + (ch->pack[1] << 13) | + (ch->port[1] << 9) | + (ch->burst[0] << 7) | + (ch->pack[0] << 6) | + (ch->port[0] << 2) | + (ch->data_type >> 1); break; case 0x02: /* SYS_DMA_CCR_CH0 */ - *value = (s->ch[ch].mode[1] << 14) | - (s->ch[ch].mode[0] << 12) | - (s->ch[ch].end_prog << 11) | - (s->ch[ch].repeat << 9) | - (s->ch[ch].auto_init << 8) | - (s->ch[ch].running << 7) | - (s->ch[ch].priority << 6) | - (s->ch[ch].fs << 5) | s->ch[ch].sync; + if (s->model == omap_dma_3_1) + *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ + else + *value = ch->omap_3_1_compatible_disable << 10; + *value |= (ch->mode[1] << 14) | + (ch->mode[0] << 12) | + (ch->end_prog << 11) | + (ch->repeat << 9) | + (ch->auto_init << 8) | + (ch->enable << 7) | + (ch->priority << 6) | + (ch->fs << 5) | ch->sync; break; case 0x04: /* SYS_DMA_CICR_CH0 */ - *value = s->ch[ch].interrupts; + *value = ch->interrupts; break; case 0x06: /* SYS_DMA_CSR_CH0 */ - /* FIXME: shared CSR for channels sharing the interrupts */ - *value = s->ch[ch].status; - s->ch[ch].status &= 0x40; - omap_dma_interrupts_update(s); + *value = ch->status; + ch->status &= SYNC; + if (!ch->omap_3_1_compatible_disable && ch->sibling) { + *value |= (ch->sibling->status & 0x3f) << 6; + ch->sibling->status &= SYNC; + } + qemu_irq_lower(ch->irq); break; case 0x08: /* SYS_DMA_CSSA_L_CH0 */ - *value = s->ch[ch].addr[0] & 0x0000ffff; + *value = ch->addr[0] & 0x0000ffff; break; case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ - *value = s->ch[ch].addr[0] >> 16; + *value = ch->addr[0] >> 16; break; case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ - *value = s->ch[ch].addr[1] & 0x0000ffff; + *value = ch->addr[1] & 0x0000ffff; break; case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ - *value = s->ch[ch].addr[1] >> 16; + *value = ch->addr[1] >> 16; break; case 0x10: /* SYS_DMA_CEN_CH0 */ - *value = s->ch[ch].elements; + *value = ch->elements; break; case 0x12: /* SYS_DMA_CFN_CH0 */ - *value = s->ch[ch].frames; + *value = ch->frames; break; case 0x14: /* SYS_DMA_CFI_CH0 */ - *value = s->ch[ch].frame_index; + *value = ch->frame_index[0]; break; case 0x16: /* SYS_DMA_CEI_CH0 */ - *value = s->ch[ch].element_index; + *value = ch->element_index[0]; + break; + + case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ + if (ch->omap_3_1_compatible_disable) + *value = ch->active_set.src & 0xffff; /* CSAC */ + else + *value = ch->cpc; + break; + + case 0x1a: /* DMA_CDAC */ + *value = ch->active_set.dest & 0xffff; /* CDAC */ + break; + + case 0x1c: /* DMA_CDEI */ + *value = ch->element_index[1]; + break; + + case 0x1e: /* DMA_CDFI */ + *value = ch->frame_index[1]; + break; + + case 0x20: /* DMA_COLOR_L */ + *value = ch->color & 0xffff; + break; + + case 0x22: /* DMA_COLOR_U */ + *value = ch->color >> 16; break; - case 0x18: /* SYS_DMA_CPC_CH0 */ - *value = s->ch[ch].cpc; + case 0x24: /* DMA_CCR2 */ + *value = (ch->bs << 2) | + (ch->transparent_copy << 1) | + ch->constant_fill; + break; + + case 0x28: /* DMA_CLNK_CTRL */ + *value = (ch->link_enabled << 15) | + (ch->link_next_ch & 0xf); + break; + + case 0x2a: /* DMA_LCH_CTRL */ + *value = (ch->interleave_disabled << 15) | + ch->type; break; default: @@ -712,226 +963,688 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, } static int omap_dma_ch_reg_write(struct omap_dma_s *s, - int ch, int reg, uint16_t value) { + struct omap_dma_channel_s *ch, int reg, uint16_t value) +{ switch (reg) { case 0x00: /* SYS_DMA_CSDP_CH0 */ - s->ch[ch].burst[1] = (value & 0xc000) >> 14; - s->ch[ch].pack[1] = (value & 0x2000) >> 13; - s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); - s->ch[ch].burst[0] = (value & 0x0180) >> 7; - s->ch[ch].pack[0] = (value & 0x0040) >> 6; - s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); - s->ch[ch].data_type = (1 << (value & 3)); - if (s->ch[ch].port[0] >= omap_dma_port_last) + ch->burst[1] = (value & 0xc000) >> 14; + ch->pack[1] = (value & 0x2000) >> 13; + ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); + ch->burst[0] = (value & 0x0180) >> 7; + ch->pack[0] = (value & 0x0040) >> 6; + ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); + ch->data_type = (1 << (value & 3)); + if (ch->port[0] >= omap_dma_port_last) printf("%s: invalid DMA port %i\n", __FUNCTION__, - s->ch[ch].port[0]); - if (s->ch[ch].port[1] >= omap_dma_port_last) + ch->port[0]); + if (ch->port[1] >= omap_dma_port_last) printf("%s: invalid DMA port %i\n", __FUNCTION__, - s->ch[ch].port[1]); + ch->port[1]); if ((value & 3) == 3) - printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch); + printf("%s: bad data_type for DMA channel\n", __FUNCTION__); break; case 0x02: /* SYS_DMA_CCR_CH0 */ - s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); - s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); - s->ch[ch].end_prog = (value & 0x0800) >> 11; - s->ch[ch].repeat = (value & 0x0200) >> 9; - s->ch[ch].auto_init = (value & 0x0100) >> 8; - s->ch[ch].priority = (value & 0x0040) >> 6; - s->ch[ch].fs = (value & 0x0020) >> 5; - s->ch[ch].sync = value & 0x001f; - if (value & 0x0080) { - if (s->ch[ch].running) { - if (!s->ch[ch].signalled && - s->ch[ch].auto_init && s->ch[ch].end_prog) - omap_dma_channel_load(s, ch); - } else { - s->ch[ch].running = 1; - omap_dma_channel_load(s, ch); - } - if (!s->ch[ch].sync || (s->drq & (1 << s->ch[ch].sync))) - omap_dma_request_run(s, ch, 0); - } else { - s->ch[ch].running = 0; - omap_dma_request_stop(s, ch); - } + ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); + ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); + ch->end_prog = (value & 0x0800) >> 11; + if (s->model > omap_dma_3_1) + ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; + ch->repeat = (value & 0x0200) >> 9; + ch->auto_init = (value & 0x0100) >> 8; + ch->priority = (value & 0x0040) >> 6; + ch->fs = (value & 0x0020) >> 5; + ch->sync = value & 0x001f; + + if (value & 0x0080) + omap_dma_enable_channel(s, ch); + else + omap_dma_disable_channel(s, ch); + + if (ch->end_prog) + omap_dma_channel_end_prog(s, ch); + break; case 0x04: /* SYS_DMA_CICR_CH0 */ - s->ch[ch].interrupts = value & 0x003f; + ch->interrupts = value; break; case 0x06: /* SYS_DMA_CSR_CH0 */ - return 1; + OMAP_RO_REG((target_phys_addr_t) reg); + break; case 0x08: /* SYS_DMA_CSSA_L_CH0 */ - s->ch[ch].addr[0] &= 0xffff0000; - s->ch[ch].addr[0] |= value; + ch->addr[0] &= 0xffff0000; + ch->addr[0] |= value; break; case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ - s->ch[ch].addr[0] &= 0x0000ffff; - s->ch[ch].addr[0] |= value << 16; + ch->addr[0] &= 0x0000ffff; + ch->addr[0] |= (uint32_t) value << 16; break; case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ - s->ch[ch].addr[1] &= 0xffff0000; - s->ch[ch].addr[1] |= value; + ch->addr[1] &= 0xffff0000; + ch->addr[1] |= value; break; case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ - s->ch[ch].addr[1] &= 0x0000ffff; - s->ch[ch].addr[1] |= value << 16; + ch->addr[1] &= 0x0000ffff; + ch->addr[1] |= (uint32_t) value << 16; break; case 0x10: /* SYS_DMA_CEN_CH0 */ - s->ch[ch].elements = value & 0xffff; + ch->elements = value; break; case 0x12: /* SYS_DMA_CFN_CH0 */ - s->ch[ch].frames = value & 0xffff; + ch->frames = value; break; case 0x14: /* SYS_DMA_CFI_CH0 */ - s->ch[ch].frame_index = value & 0xffff; + ch->frame_index[0] = (int16_t) value; break; case 0x16: /* SYS_DMA_CEI_CH0 */ - s->ch[ch].element_index = value & 0xffff; + ch->element_index[0] = (int16_t) value; break; - case 0x18: /* SYS_DMA_CPC_CH0 */ - return 1; + case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ + OMAP_RO_REG((target_phys_addr_t) reg); + break; + + case 0x1c: /* DMA_CDEI */ + ch->element_index[1] = (int16_t) value; + break; + + case 0x1e: /* DMA_CDFI */ + ch->frame_index[1] = (int16_t) value; + break; + + case 0x20: /* DMA_COLOR_L */ + ch->color &= 0xffff0000; + ch->color |= value; + break; + + case 0x22: /* DMA_COLOR_U */ + ch->color &= 0xffff; + ch->color |= value << 16; + break; + + case 0x24: /* DMA_CCR2 */ + ch->bs = (value >> 2) & 0x1; + ch->transparent_copy = (value >> 1) & 0x1; + ch->constant_fill = value & 0x1; + break; + + case 0x28: /* DMA_CLNK_CTRL */ + ch->link_enabled = (value >> 15) & 0x1; + if (value & (1 << 14)) { /* Stop_Lnk */ + ch->link_enabled = 0; + omap_dma_disable_channel(s, ch); + } + ch->link_next_ch = value & 0x1f; + break; + + case 0x2a: /* DMA_LCH_CTRL */ + ch->interleave_disabled = (value >> 15) & 0x1; + ch->type = value & 0xf; + break; default: - OMAP_BAD_REG((unsigned long) reg); + return 1; } return 0; } -static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) +static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, + uint16_t value) { - struct omap_dma_s *s = (struct omap_dma_s *) opaque; - int i, reg, ch, offset = addr - s->base; - uint16_t ret; + switch (offset) { + case 0xbc0: /* DMA_LCD_CSDP */ + s->brust_f2 = (value >> 14) & 0x3; + s->pack_f2 = (value >> 13) & 0x1; + s->data_type_f2 = (1 << ((value >> 11) & 0x3)); + s->brust_f1 = (value >> 7) & 0x3; + s->pack_f1 = (value >> 6) & 0x1; + s->data_type_f1 = (1 << ((value >> 0) & 0x3)); + break; + + case 0xbc2: /* DMA_LCD_CCR */ + s->mode_f2 = (value >> 14) & 0x3; + s->mode_f1 = (value >> 12) & 0x3; + s->end_prog = (value >> 11) & 0x1; + s->omap_3_1_compatible_disable = (value >> 10) & 0x1; + s->repeat = (value >> 9) & 0x1; + s->auto_init = (value >> 8) & 0x1; + s->running = (value >> 7) & 0x1; + s->priority = (value >> 6) & 0x1; + s->bs = (value >> 4) & 0x1; + break; + + case 0xbc4: /* DMA_LCD_CTRL */ + s->dst = (value >> 8) & 0x1; + s->src = ((value >> 6) & 0x3) << 1; + s->condition = 0; + /* Assume no bus errors and thus no BUS_ERROR irq bits. */ + s->interrupts = (value >> 1) & 1; + s->dual = value & 1; + break; + + case 0xbc8: /* TOP_B1_L */ + s->src_f1_top &= 0xffff0000; + s->src_f1_top |= 0x0000ffff & value; + break; + + case 0xbca: /* TOP_B1_U */ + s->src_f1_top &= 0x0000ffff; + s->src_f1_top |= value << 16; + break; + case 0xbcc: /* BOT_B1_L */ + s->src_f1_bottom &= 0xffff0000; + s->src_f1_bottom |= 0x0000ffff & value; + break; + + case 0xbce: /* BOT_B1_U */ + s->src_f1_bottom &= 0x0000ffff; + s->src_f1_bottom |= (uint32_t) value << 16; + break; + + case 0xbd0: /* TOP_B2_L */ + s->src_f2_top &= 0xffff0000; + s->src_f2_top |= 0x0000ffff & value; + break; + + case 0xbd2: /* TOP_B2_U */ + s->src_f2_top &= 0x0000ffff; + s->src_f2_top |= (uint32_t) value << 16; + break; + + case 0xbd4: /* BOT_B2_L */ + s->src_f2_bottom &= 0xffff0000; + s->src_f2_bottom |= 0x0000ffff & value; + break; + + case 0xbd6: /* BOT_B2_U */ + s->src_f2_bottom &= 0x0000ffff; + s->src_f2_bottom |= (uint32_t) value << 16; + break; + + case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ + s->element_index_f1 = value; + break; + + case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ + s->frame_index_f1 &= 0xffff0000; + s->frame_index_f1 |= 0x0000ffff & value; + break; + + case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ + s->frame_index_f1 &= 0x0000ffff; + s->frame_index_f1 |= (uint32_t) value << 16; + break; + + case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ + s->element_index_f2 = value; + break; + + case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ + s->frame_index_f2 &= 0xffff0000; + s->frame_index_f2 |= 0x0000ffff & value; + break; + + case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ + s->frame_index_f2 &= 0x0000ffff; + s->frame_index_f2 |= (uint32_t) value << 16; + break; + + case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ + s->elements_f1 = value; + break; + + case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ + s->frames_f1 = value; + break; + + case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ + s->elements_f2 = value; + break; + + case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ + s->frames_f2 = value; + break; + + case 0xbea: /* DMA_LCD_LCH_CTRL */ + s->lch_type = value & 0xf; + break; + + default: + return 1; + } + return 0; +} + +static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, + uint16_t *ret) +{ switch (offset) { - case 0x000 ... 0x2fe: - reg = offset & 0x3f; - ch = (offset >> 6) & 0x0f; - if (omap_dma_ch_reg_read(s, ch, reg, &ret)) - break; - return ret; + case 0xbc0: /* DMA_LCD_CSDP */ + *ret = (s->brust_f2 << 14) | + (s->pack_f2 << 13) | + ((s->data_type_f2 >> 1) << 11) | + (s->brust_f1 << 7) | + (s->pack_f1 << 6) | + ((s->data_type_f1 >> 1) << 0); + break; + + case 0xbc2: /* DMA_LCD_CCR */ + *ret = (s->mode_f2 << 14) | + (s->mode_f1 << 12) | + (s->end_prog << 11) | + (s->omap_3_1_compatible_disable << 10) | + (s->repeat << 9) | + (s->auto_init << 8) | + (s->running << 7) | + (s->priority << 6) | + (s->bs << 4); + break; + + case 0xbc4: /* DMA_LCD_CTRL */ + qemu_irq_lower(s->irq); + *ret = (s->dst << 8) | + ((s->src & 0x6) << 5) | + (s->condition << 3) | + (s->interrupts << 1) | + s->dual; + break; + + case 0xbc8: /* TOP_B1_L */ + *ret = s->src_f1_top & 0xffff; + break; + + case 0xbca: /* TOP_B1_U */ + *ret = s->src_f1_top >> 16; + break; + + case 0xbcc: /* BOT_B1_L */ + *ret = s->src_f1_bottom & 0xffff; + break; + + case 0xbce: /* BOT_B1_U */ + *ret = s->src_f1_bottom >> 16; + break; + + case 0xbd0: /* TOP_B2_L */ + *ret = s->src_f2_top & 0xffff; + break; + + case 0xbd2: /* TOP_B2_U */ + *ret = s->src_f2_top >> 16; + break; + + case 0xbd4: /* BOT_B2_L */ + *ret = s->src_f2_bottom & 0xffff; + break; + + case 0xbd6: /* BOT_B2_U */ + *ret = s->src_f2_bottom >> 16; + break; + + case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ + *ret = s->element_index_f1; + break; + + case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ + *ret = s->frame_index_f1 & 0xffff; + break; + + case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ + *ret = s->frame_index_f1 >> 16; + break; + + case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ + *ret = s->element_index_f2; + break; + + case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ + *ret = s->frame_index_f2 & 0xffff; + break; + + case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ + *ret = s->frame_index_f2 >> 16; + break; + + case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ + *ret = s->elements_f1; + break; + case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ + *ret = s->frames_f1; + break; + + case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ + *ret = s->elements_f2; + break; + + case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ + *ret = s->frames_f2; + break; + + case 0xbea: /* DMA_LCD_LCH_CTRL */ + *ret = s->lch_type; + break; + + default: + return 1; + } + return 0; +} + +static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, + uint16_t value) +{ + switch (offset) { case 0x300: /* SYS_DMA_LCD_CTRL */ - i = s->lcd_ch.condition; - s->lcd_ch.condition = 0; - qemu_irq_lower(s->lcd_ch.irq); - return ((s->lcd_ch.src == imif) << 6) | (i << 3) | - (s->lcd_ch.interrupts << 1) | s->lcd_ch.dual; + s->src = (value & 0x40) ? imif : emiff; + s->condition = 0; + /* Assume no bus errors and thus no BUS_ERROR irq bits. */ + s->interrupts = (value >> 1) & 1; + s->dual = value & 1; + break; case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ - return s->lcd_ch.src_f1_top & 0xffff; + s->src_f1_top &= 0xffff0000; + s->src_f1_top |= 0x0000ffff & value; + break; case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ - return s->lcd_ch.src_f1_top >> 16; + s->src_f1_top &= 0x0000ffff; + s->src_f1_top |= value << 16; + break; case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ - return s->lcd_ch.src_f1_bottom & 0xffff; + s->src_f1_bottom &= 0xffff0000; + s->src_f1_bottom |= 0x0000ffff & value; + break; case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ - return s->lcd_ch.src_f1_bottom >> 16; + s->src_f1_bottom &= 0x0000ffff; + s->src_f1_bottom |= value << 16; + break; case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ - return s->lcd_ch.src_f2_top & 0xffff; + s->src_f2_top &= 0xffff0000; + s->src_f2_top |= 0x0000ffff & value; + break; case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ - return s->lcd_ch.src_f2_top >> 16; + s->src_f2_top &= 0x0000ffff; + s->src_f2_top |= value << 16; + break; case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ - return s->lcd_ch.src_f2_bottom & 0xffff; + s->src_f2_bottom &= 0xffff0000; + s->src_f2_bottom |= 0x0000ffff & value; + break; case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ - return s->lcd_ch.src_f2_bottom >> 16; + s->src_f2_bottom &= 0x0000ffff; + s->src_f2_bottom |= value << 16; + break; - case 0x400: /* SYS_DMA_GCR */ - return s->gcr; + default: + return 1; } - - OMAP_BAD_REG(addr); return 0; } -static void omap_dma_write(void *opaque, target_phys_addr_t addr, - uint32_t value) +static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, + uint16_t *ret) { - struct omap_dma_s *s = (struct omap_dma_s *) opaque; - int reg, ch, offset = addr - s->base; + int i; switch (offset) { - case 0x000 ... 0x2fe: - reg = offset & 0x3f; - ch = (offset >> 6) & 0x0f; - if (omap_dma_ch_reg_write(s, ch, reg, value)) - OMAP_RO_REG(addr); - break; - case 0x300: /* SYS_DMA_LCD_CTRL */ - s->lcd_ch.src = (value & 0x40) ? imif : emiff; - s->lcd_ch.condition = 0; - /* Assume no bus errors and thus no BUS_ERROR irq bits. */ - s->lcd_ch.interrupts = (value >> 1) & 1; - s->lcd_ch.dual = value & 1; + i = s->condition; + s->condition = 0; + qemu_irq_lower(s->irq); + *ret = ((s->src == imif) << 6) | (i << 3) | + (s->interrupts << 1) | s->dual; break; case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ - s->lcd_ch.src_f1_top &= 0xffff0000; - s->lcd_ch.src_f1_top |= 0x0000ffff & value; + *ret = s->src_f1_top & 0xffff; break; case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ - s->lcd_ch.src_f1_top &= 0x0000ffff; - s->lcd_ch.src_f1_top |= value << 16; + *ret = s->src_f1_top >> 16; break; case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ - s->lcd_ch.src_f1_bottom &= 0xffff0000; - s->lcd_ch.src_f1_bottom |= 0x0000ffff & value; + *ret = s->src_f1_bottom & 0xffff; break; case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ - s->lcd_ch.src_f1_bottom &= 0x0000ffff; - s->lcd_ch.src_f1_bottom |= value << 16; + *ret = s->src_f1_bottom >> 16; break; case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ - s->lcd_ch.src_f2_top &= 0xffff0000; - s->lcd_ch.src_f2_top |= 0x0000ffff & value; + *ret = s->src_f2_top & 0xffff; break; case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ - s->lcd_ch.src_f2_top &= 0x0000ffff; - s->lcd_ch.src_f2_top |= value << 16; + *ret = s->src_f2_top >> 16; break; case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ - s->lcd_ch.src_f2_bottom &= 0xffff0000; - s->lcd_ch.src_f2_bottom |= 0x0000ffff & value; + *ret = s->src_f2_bottom & 0xffff; break; case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ - s->lcd_ch.src_f2_bottom &= 0x0000ffff; - s->lcd_ch.src_f2_bottom |= value << 16; + *ret = s->src_f2_bottom >> 16; break; + default: + return 1; + } + return 0; +} + +static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) +{ + switch (offset) { case 0x400: /* SYS_DMA_GCR */ - s->gcr = value & 0x000c; + s->gcr = value; + break; + + case 0x404: /* DMA_GSCR */ + if (value & 0x8) + omap_dma_disable_3_1_mapping(s); + else + omap_dma_enable_3_1_mapping(s); + break; + + case 0x408: /* DMA_GRST */ + if (value & 0x1) + omap_dma_reset(s); break; default: - OMAP_BAD_REG(addr); + return 1; } + return 0; +} + +static int omap_dma_sys_read(struct omap_dma_s *s, int offset, + uint16_t *ret) +{ + switch (offset) { + case 0x400: /* SYS_DMA_GCR */ + *ret = s->gcr; + break; + + case 0x404: /* DMA_GSCR */ + *ret = s->omap_3_1_mapping_disabled << 3; + break; + + case 0x408: /* DMA_GRST */ + *ret = 0; + break; + + case 0x442: /* DMA_HW_ID */ + case 0x444: /* DMA_PCh2_ID */ + case 0x446: /* DMA_PCh0_ID */ + case 0x448: /* DMA_PCh1_ID */ + case 0x44a: /* DMA_PChG_ID */ + case 0x44c: /* DMA_PChD_ID */ + *ret = 1; + break; + + case 0x44e: /* DMA_CAPS_0_U */ + *ret = (1 << 3) | /* Constant Fill Capacity */ + (1 << 2); /* Transparent BLT Capacity */ + break; + + case 0x450: /* DMA_CAPS_0_L */ + case 0x452: /* DMA_CAPS_1_U */ + *ret = 0; + break; + + case 0x454: /* DMA_CAPS_1_L */ + *ret = (1 << 1); /* 1-bit palletized capability */ + break; + + case 0x456: /* DMA_CAPS_2 */ + *ret = (1 << 8) | /* SSDIC */ + (1 << 7) | /* DDIAC */ + (1 << 6) | /* DSIAC */ + (1 << 5) | /* DPIAC */ + (1 << 4) | /* DCAC */ + (1 << 3) | /* SDIAC */ + (1 << 2) | /* SSIAC */ + (1 << 1) | /* SPIAC */ + 1; /* SCAC */ + break; + + case 0x458: /* DMA_CAPS_3 */ + *ret = (1 << 5) | /* CCC */ + (1 << 4) | /* IC */ + (1 << 3) | /* ARC */ + (1 << 2) | /* AEC */ + (1 << 1) | /* FSC */ + 1; /* ESC */ + break; + + case 0x45a: /* DMA_CAPS_4 */ + *ret = (1 << 6) | /* SSC */ + (1 << 5) | /* BIC */ + (1 << 4) | /* LFIC */ + (1 << 3) | /* FIC */ + (1 << 2) | /* HFIC */ + (1 << 1) | /* EDIC */ + 1; /* TOIC */ + break; + + case 0x460: /* DMA_PCh2_SR */ + case 0x480: /* DMA_PCh0_SR */ + case 0x482: /* DMA_PCh1_SR */ + case 0x4c0: /* DMA_PChD_SR_0 */ + printf("%s: Physical Channel Status Registers not implemented.\n", + __FUNCTION__); + *ret = 0xff; + break; + + default: + return 1; + } + return 0; +} + +static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_dma_s *s = (struct omap_dma_s *) opaque; + int reg, ch, offset = addr - s->base; + uint16_t ret; + + switch (offset) { + case 0x300 ... 0x3fe: + if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { + if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret)) + break; + return ret; + } + /* Fall through. */ + case 0x000 ... 0x2fe: + reg = offset & 0x3f; + ch = (offset >> 6) & 0x0f; + if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret)) + break; + return ret; + + case 0x404 ... 0x4fe: + if (s->model == omap_dma_3_1) + break; + /* Fall through. */ + case 0x400: + if (omap_dma_sys_read(s, offset, &ret)) + break; + return ret; + + case 0xb00 ... 0xbfe: + if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { + if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret)) + break; + return ret; + } + break; + } + + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_dma_write(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_dma_s *s = (struct omap_dma_s *) opaque; + int reg, ch, offset = addr - s->base; + + switch (offset) { + case 0x300 ... 0x3fe: + if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { + if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value)) + break; + return; + } + /* Fall through. */ + case 0x000 ... 0x2fe: + reg = offset & 0x3f; + ch = (offset >> 6) & 0x0f; + if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value)) + break; + return; + + case 0x404 ... 0x4fe: + if (s->model == omap_dma_3_1) + break; + case 0x400: + /* Fall through. */ + if (omap_dma_sys_write(s, offset, value)) + break; + return; + + case 0xb00 ... 0xbfe: + if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { + if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value)) + break; + return; + } + break; + } + + OMAP_BAD_REG(addr); } static CPUReadMemoryFunc *omap_dma_readfn[] = { @@ -953,7 +1666,7 @@ static void omap_dma_request(void *opaque, int drq, int req) if (req) { if (~s->drq & (1 << drq)) { s->drq |= 1 << drq; - omap_dma_request_run(s, 0, drq); + omap_dma_process_request(s, drq); } } else s->drq &= ~(1 << drq); @@ -964,7 +1677,8 @@ static void omap_dma_clk_update(void *opaque, int line, int on) struct omap_dma_s *s = (struct omap_dma_s *) opaque; if (on) { - s->delay = ticks_per_sec >> 5; + /* TODO: make a clever calculation */ + s->delay = ticks_per_sec >> 8; if (s->run_count) qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); } else { @@ -973,37 +1687,33 @@ static void omap_dma_clk_update(void *opaque, int line, int on) } } -static void omap_dma_reset(struct omap_dma_s *s) -{ - int i; - - qemu_del_timer(s->tm); - s->gcr = 0x0004; - s->drq = 0x00000000; - s->run_count = 0; - s->lcd_ch.src = emiff; - s->lcd_ch.condition = 0; - s->lcd_ch.interrupts = 0; - s->lcd_ch.dual = 0; - memset(s->ch, 0, sizeof(s->ch)); - for (i = 0; i < s->chans; i ++) - s->ch[i].interrupts = 0x0003; -} - -struct omap_dma_s *omap_dma_init(target_phys_addr_t base, - qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk) +struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, + qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, + enum omap_dma_model model) { - int iomemtype; + int iomemtype, num_irqs, memsize, i; struct omap_dma_s *s = (struct omap_dma_s *) qemu_mallocz(sizeof(struct omap_dma_s)); - s->ih = pic; + if (model == omap_dma_3_1) { + num_irqs = 6; + memsize = 0x800; + } else { + num_irqs = 16; + memsize = 0xc00; + } s->base = base; - s->chans = 9; + s->model = model; s->mpu = mpu; s->clk = clk; - s->lcd_ch.irq = pic[OMAP_INT_DMA_LCD]; + s->lcd_ch.irq = lcd_irq; s->lcd_ch.mpu = mpu; + while (num_irqs --) + s->ch[num_irqs].irq = irqs[num_irqs]; + for (i = 0; i < 3; i ++) { + s->ch[i].sibling = &s->ch[i + 6]; + s->ch[i + 6].sibling = &s->ch[i]; + } s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32); @@ -1012,43 +1722,43 @@ struct omap_dma_s *omap_dma_init(target_phys_addr_t base, iomemtype = cpu_register_io_memory(0, omap_dma_readfn, omap_dma_writefn, s); - cpu_register_physical_memory(s->base, 0x800, iomemtype); + cpu_register_physical_memory(s->base, memsize, iomemtype); return s; } /* DMA ports */ -int omap_validate_emiff_addr(struct omap_mpu_state_s *s, +static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, target_phys_addr_t addr) { return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size; } -int omap_validate_emifs_addr(struct omap_mpu_state_s *s, +static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, target_phys_addr_t addr) { return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE; } -int omap_validate_imif_addr(struct omap_mpu_state_s *s, +static int omap_validate_imif_addr(struct omap_mpu_state_s *s, target_phys_addr_t addr) { return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size; } -int omap_validate_tipb_addr(struct omap_mpu_state_s *s, +static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, target_phys_addr_t addr) { return addr >= 0xfffb0000 && addr < 0xffff0000; } -int omap_validate_local_addr(struct omap_mpu_state_s *s, +static int omap_validate_local_addr(struct omap_mpu_state_s *s, target_phys_addr_t addr) { return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; } -int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, +static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, target_phys_addr_t addr) { return addr >= 0xe1010000 && addr < 0xe1020004; @@ -1095,9 +1805,24 @@ static inline void omap_timer_update(struct omap_mpu_timer_s *timer) if (timer->enable && timer->st && timer->rate) { timer->val = timer->reset_val; /* Should skip this on clk enable */ - expires = timer->time + muldiv64(timer->val << (timer->ptv + 1), + expires = muldiv64(timer->val << (timer->ptv + 1), ticks_per_sec, timer->rate); - qemu_mod_timer(timer->timer, expires); + + /* If timer expiry would be sooner than in about 1 ms and + * auto-reload isn't set, then fire immediately. This is a hack + * to make systems like PalmOS run in acceptable time. PalmOS + * sets the interval to a very low value and polls the status bit + * in a busy loop when it wants to sleep just a couple of CPU + * ticks. */ + if (expires > (ticks_per_sec >> 10) || timer->ar) + qemu_mod_timer(timer->timer, timer->time + expires); + else { + timer->val = 0; + timer->st = 0; + if (timer->it_ena) + /* Edge-triggered irq */ + qemu_irq_pulse(timer->irq); + } } else qemu_del_timer(timer->timer); } @@ -1113,7 +1838,8 @@ static void omap_timer_tick(void *opaque) } if (timer->it_ena) - qemu_irq_raise(timer->irq); + /* Edge-triggered irq */ + qemu_irq_pulse(timer->irq); omap_timer_update(timer); } @@ -1283,8 +2009,10 @@ static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, s->mode |= (value >> 15) & 1; if (s->last_wr == 0xf5) { if ((value & 0xff) == 0xa0) { - s->mode = 0; - omap_clk_put(s->timer.clk); + if (s->mode) { + s->mode = 0; + omap_clk_put(s->timer.clk); + } } else { /* XXX: on T|E hardware somehow this has no effect, * on Zire 71 it works as specified. */ @@ -1359,7 +2087,7 @@ struct omap_32khz_timer_s { static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) { struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; - int offset = addr - s->timer.base; + int offset = addr & OMAP_MPUI_REG_MASK; switch (offset) { case 0x00: /* TVR */ @@ -1382,7 +2110,7 @@ static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, uint32_t value) { struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; - int offset = addr - s->timer.base; + int offset = addr & OMAP_MPUI_REG_MASK; switch (offset) { case 0x00: /* TVR */ @@ -2175,23 +2903,23 @@ static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) uint32_t ret; switch (offset) { - case 0xfffecc00: /* IMIF_PRIO */ - case 0xfffecc04: /* EMIFS_PRIO */ - case 0xfffecc08: /* EMIFF_PRIO */ - case 0xfffecc0c: /* EMIFS_CONFIG */ - case 0xfffecc10: /* EMIFS_CS0_CONFIG */ - case 0xfffecc14: /* EMIFS_CS1_CONFIG */ - case 0xfffecc18: /* EMIFS_CS2_CONFIG */ - case 0xfffecc1c: /* EMIFS_CS3_CONFIG */ - case 0xfffecc24: /* EMIFF_MRS */ - case 0xfffecc28: /* TIMEOUT1 */ - case 0xfffecc2c: /* TIMEOUT2 */ - case 0xfffecc30: /* TIMEOUT3 */ - case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */ - case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */ + case 0x00: /* IMIF_PRIO */ + case 0x04: /* EMIFS_PRIO */ + case 0x08: /* EMIFF_PRIO */ + case 0x0c: /* EMIFS_CONFIG */ + case 0x10: /* EMIFS_CS0_CONFIG */ + case 0x14: /* EMIFS_CS1_CONFIG */ + case 0x18: /* EMIFS_CS2_CONFIG */ + case 0x1c: /* EMIFS_CS3_CONFIG */ + case 0x24: /* EMIFF_MRS */ + case 0x28: /* TIMEOUT1 */ + case 0x2c: /* TIMEOUT2 */ + case 0x30: /* TIMEOUT3 */ + case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ + case 0x40: /* EMIFS_CFG_DYN_WAIT */ return s->tcmi_regs[offset >> 2]; - case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */ + case 0x20: /* EMIFF_SDRAM_CONFIG */ ret = s->tcmi_regs[offset >> 2]; s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ /* XXX: We can try using the VGA_DIRTY flag for this */ @@ -2209,23 +2937,23 @@ static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, int offset = addr - s->tcmi_base; switch (offset) { - case 0xfffecc00: /* IMIF_PRIO */ - case 0xfffecc04: /* EMIFS_PRIO */ - case 0xfffecc08: /* EMIFF_PRIO */ - case 0xfffecc10: /* EMIFS_CS0_CONFIG */ - case 0xfffecc14: /* EMIFS_CS1_CONFIG */ - case 0xfffecc18: /* EMIFS_CS2_CONFIG */ - case 0xfffecc1c: /* EMIFS_CS3_CONFIG */ - case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */ - case 0xfffecc24: /* EMIFF_MRS */ - case 0xfffecc28: /* TIMEOUT1 */ - case 0xfffecc2c: /* TIMEOUT2 */ - case 0xfffecc30: /* TIMEOUT3 */ - case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */ - case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */ + case 0x00: /* IMIF_PRIO */ + case 0x04: /* EMIFS_PRIO */ + case 0x08: /* EMIFF_PRIO */ + case 0x10: /* EMIFS_CS0_CONFIG */ + case 0x14: /* EMIFS_CS1_CONFIG */ + case 0x18: /* EMIFS_CS2_CONFIG */ + case 0x1c: /* EMIFS_CS3_CONFIG */ + case 0x20: /* EMIFF_SDRAM_CONFIG */ + case 0x24: /* EMIFF_MRS */ + case 0x28: /* TIMEOUT1 */ + case 0x2c: /* TIMEOUT2 */ + case 0x30: /* TIMEOUT3 */ + case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ + case 0x40: /* EMIFS_CFG_DYN_WAIT */ s->tcmi_regs[offset >> 2] = value; break; - case 0xfffecc0c: /* EMIFS_CONFIG */ + case 0x0c: /* EMIFS_CONFIG */ s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4); break; @@ -2399,7 +3127,7 @@ static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) return s->clkm.arm_rstct2; case 0x18: /* ARM_SYSST */ - return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start; + return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; case 0x1c: /* ARM_CKOUT1 */ return s->clkm.arm_ckout1; @@ -2678,7 +3406,7 @@ static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) return s->clkm.dsp_rstct2; case 0x18: /* DSP_SYSST */ - return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start | + return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | (s->env->halted << 6); /* Quite useless... */ } @@ -2754,9 +3482,9 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s) s->clkm.clocking_scheme = 0; omap_clkm_ckctl_update(s, ~0, 0x3000); s->clkm.arm_ckctl = 0x3000; - omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 & 0x0400, 0x0400); + omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); s->clkm.arm_idlect1 = 0x0400; - omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 & 0x0100, 0x0100); + omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); s->clkm.arm_idlect2 = 0x0100; s->clkm.arm_ewupct = 0x003f; s->clkm.arm_rstct1 = 0x0000; @@ -2780,19 +3508,1988 @@ static void omap_clkm_init(target_phys_addr_t mpu_base, s->clkm.mpu_base = mpu_base; s->clkm.dsp_base = dsp_base; - s->clkm.cold_start = 0x3a; + s->clkm.arm_idlect1 = 0x03ff; + s->clkm.arm_idlect2 = 0x0100; + s->clkm.dsp_idlect1 = 0x0002; omap_clkm_reset(s); + s->clkm.cold_start = 0x3a; cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]); cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]); } +/* MPU I/O */ +struct omap_mpuio_s { + target_phys_addr_t base; + qemu_irq irq; + qemu_irq kbd_irq; + qemu_irq *in; + qemu_irq handler[16]; + qemu_irq wakeup; + + uint16_t inputs; + uint16_t outputs; + uint16_t dir; + uint16_t edge; + uint16_t mask; + uint16_t ints; + + uint16_t debounce; + uint16_t latch; + uint8_t event; + + uint8_t buttons[5]; + uint8_t row_latch; + uint8_t cols; + int kbd_mask; + int clk; +}; + +static void omap_mpuio_set(void *opaque, int line, int level) +{ + struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; + uint16_t prev = s->inputs; + + if (level) + s->inputs |= 1 << line; + else + s->inputs &= ~(1 << line); + + if (((1 << line) & s->dir & ~s->mask) && s->clk) { + if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { + s->ints |= 1 << line; + qemu_irq_raise(s->irq); + /* TODO: wakeup */ + } + if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ + (s->event >> 1) == line) /* PIN_SELECT */ + s->latch = s->inputs; + } +} + +static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) +{ + int i; + uint8_t *row, rows = 0, cols = ~s->cols; + + for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) + if (*row & cols) + rows |= i; + + qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); + s->row_latch = ~rows; +} + +static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + uint16_t ret; + + switch (offset) { + case 0x00: /* INPUT_LATCH */ + return s->inputs; + + case 0x04: /* OUTPUT_REG */ + return s->outputs; + + case 0x08: /* IO_CNTL */ + return s->dir; + + case 0x10: /* KBR_LATCH */ + return s->row_latch; + + case 0x14: /* KBC_REG */ + return s->cols; + + case 0x18: /* GPIO_EVENT_MODE_REG */ + return s->event; + + case 0x1c: /* GPIO_INT_EDGE_REG */ + return s->edge; + + case 0x20: /* KBD_INT */ + return (~s->row_latch & 0x1f) && !s->kbd_mask; + + case 0x24: /* GPIO_INT */ + ret = s->ints; + s->ints &= s->mask; + if (ret) + qemu_irq_lower(s->irq); + return ret; + + case 0x28: /* KBD_MASKIT */ + return s->kbd_mask; + + case 0x2c: /* GPIO_MASKIT */ + return s->mask; + + case 0x30: /* GPIO_DEBOUNCING_REG */ + return s->debounce; + + case 0x34: /* GPIO_LATCH_REG */ + return s->latch; + } + + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + uint16_t diff; + int ln; + + switch (offset) { + case 0x04: /* OUTPUT_REG */ + diff = (s->outputs ^ value) & ~s->dir; + s->outputs = value; + while ((ln = ffs(diff))) { + ln --; + if (s->handler[ln]) + qemu_set_irq(s->handler[ln], (value >> ln) & 1); + diff &= ~(1 << ln); + } + break; + + case 0x08: /* IO_CNTL */ + diff = s->outputs & (s->dir ^ value); + s->dir = value; + + value = s->outputs & ~s->dir; + while ((ln = ffs(diff))) { + ln --; + if (s->handler[ln]) + qemu_set_irq(s->handler[ln], (value >> ln) & 1); + diff &= ~(1 << ln); + } + break; + + case 0x14: /* KBC_REG */ + s->cols = value; + omap_mpuio_kbd_update(s); + break; + + case 0x18: /* GPIO_EVENT_MODE_REG */ + s->event = value & 0x1f; + break; + + case 0x1c: /* GPIO_INT_EDGE_REG */ + s->edge = value; + break; + + case 0x28: /* KBD_MASKIT */ + s->kbd_mask = value & 1; + omap_mpuio_kbd_update(s); + break; + + case 0x2c: /* GPIO_MASKIT */ + s->mask = value; + break; + + case 0x30: /* GPIO_DEBOUNCING_REG */ + s->debounce = value & 0x1ff; + break; + + case 0x00: /* INPUT_LATCH */ + case 0x10: /* KBR_LATCH */ + case 0x20: /* KBD_INT */ + case 0x24: /* GPIO_INT */ + case 0x34: /* GPIO_LATCH_REG */ + OMAP_RO_REG(addr); + return; + + default: + OMAP_BAD_REG(addr); + return; + } +} + +static CPUReadMemoryFunc *omap_mpuio_readfn[] = { + omap_badwidth_read16, + omap_mpuio_read, + omap_badwidth_read16, +}; + +static CPUWriteMemoryFunc *omap_mpuio_writefn[] = { + omap_badwidth_write16, + omap_mpuio_write, + omap_badwidth_write16, +}; + +static void omap_mpuio_reset(struct omap_mpuio_s *s) +{ + s->inputs = 0; + s->outputs = 0; + s->dir = ~0; + s->event = 0; + s->edge = 0; + s->kbd_mask = 0; + s->mask = 0; + s->debounce = 0; + s->latch = 0; + s->ints = 0; + s->row_latch = 0x1f; + s->clk = 1; +} + +static void omap_mpuio_onoff(void *opaque, int line, int on) +{ + struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; + + s->clk = on; + if (on) + omap_mpuio_kbd_update(s); +} + +struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base, + qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, + omap_clk clk) +{ + int iomemtype; + struct omap_mpuio_s *s = (struct omap_mpuio_s *) + qemu_mallocz(sizeof(struct omap_mpuio_s)); + + s->base = base; + s->irq = gpio_int; + s->kbd_irq = kbd_int; + s->wakeup = wakeup; + s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); + omap_mpuio_reset(s); + + iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn, + omap_mpuio_writefn, s); + cpu_register_physical_memory(s->base, 0x800, iomemtype); + + omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); + + return s; +} + +qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) +{ + return s->in; +} + +void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) +{ + if (line >= 16 || line < 0) + cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line); + s->handler[line] = handler; +} + +void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) +{ + if (row >= 5 || row < 0) + cpu_abort(cpu_single_env, "%s: No key %i-%i\n", + __FUNCTION__, col, row); + + if (down) + s->buttons[row] |= 1 << col; + else + s->buttons[row] &= ~(1 << col); + + omap_mpuio_kbd_update(s); +} + +/* General-Purpose I/O */ +struct omap_gpio_s { + target_phys_addr_t base; + qemu_irq irq; + qemu_irq *in; + qemu_irq handler[16]; + + uint16_t inputs; + uint16_t outputs; + uint16_t dir; + uint16_t edge; + uint16_t mask; + uint16_t ints; + uint16_t pins; +}; + +static void omap_gpio_set(void *opaque, int line, int level) +{ + struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; + uint16_t prev = s->inputs; + + if (level) + s->inputs |= 1 << line; + else + s->inputs &= ~(1 << line); + + if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & + (1 << line) & s->dir & ~s->mask) { + s->ints |= 1 << line; + qemu_irq_raise(s->irq); + } +} + +static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* DATA_INPUT */ + return s->inputs & s->pins; + + case 0x04: /* DATA_OUTPUT */ + return s->outputs; + + case 0x08: /* DIRECTION_CONTROL */ + return s->dir; + + case 0x0c: /* INTERRUPT_CONTROL */ + return s->edge; + + case 0x10: /* INTERRUPT_MASK */ + return s->mask; + + case 0x14: /* INTERRUPT_STATUS */ + return s->ints; + + case 0x18: /* PIN_CONTROL (not in OMAP310) */ + OMAP_BAD_REG(addr); + return s->pins; + } + + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_gpio_write(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + uint16_t diff; + int ln; + + switch (offset) { + case 0x00: /* DATA_INPUT */ + OMAP_RO_REG(addr); + return; + + case 0x04: /* DATA_OUTPUT */ + diff = (s->outputs ^ value) & ~s->dir; + s->outputs = value; + while ((ln = ffs(diff))) { + ln --; + if (s->handler[ln]) + qemu_set_irq(s->handler[ln], (value >> ln) & 1); + diff &= ~(1 << ln); + } + break; + + case 0x08: /* DIRECTION_CONTROL */ + diff = s->outputs & (s->dir ^ value); + s->dir = value; + + value = s->outputs & ~s->dir; + while ((ln = ffs(diff))) { + ln --; + if (s->handler[ln]) + qemu_set_irq(s->handler[ln], (value >> ln) & 1); + diff &= ~(1 << ln); + } + break; + + case 0x0c: /* INTERRUPT_CONTROL */ + s->edge = value; + break; + + case 0x10: /* INTERRUPT_MASK */ + s->mask = value; + break; + + case 0x14: /* INTERRUPT_STATUS */ + s->ints &= ~value; + if (!s->ints) + qemu_irq_lower(s->irq); + break; + + case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ + OMAP_BAD_REG(addr); + s->pins = value; + break; + + default: + OMAP_BAD_REG(addr); + return; + } +} + +/* *Some* sources say the memory region is 32-bit. */ +static CPUReadMemoryFunc *omap_gpio_readfn[] = { + omap_badwidth_read16, + omap_gpio_read, + omap_badwidth_read16, +}; + +static CPUWriteMemoryFunc *omap_gpio_writefn[] = { + omap_badwidth_write16, + omap_gpio_write, + omap_badwidth_write16, +}; + +static void omap_gpio_reset(struct omap_gpio_s *s) +{ + s->inputs = 0; + s->outputs = ~0; + s->dir = ~0; + s->edge = ~0; + s->mask = ~0; + s->ints = 0; + s->pins = ~0; +} + +struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base, + qemu_irq irq, omap_clk clk) +{ + int iomemtype; + struct omap_gpio_s *s = (struct omap_gpio_s *) + qemu_mallocz(sizeof(struct omap_gpio_s)); + + s->base = base; + s->irq = irq; + s->in = qemu_allocate_irqs(omap_gpio_set, s, 16); + omap_gpio_reset(s); + + iomemtype = cpu_register_io_memory(0, omap_gpio_readfn, + omap_gpio_writefn, s); + cpu_register_physical_memory(s->base, 0x1000, iomemtype); + + return s; +} + +qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s) +{ + return s->in; +} + +void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler) +{ + if (line >= 16 || line < 0) + cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line); + s->handler[line] = handler; +} + +/* MicroWire Interface */ +struct omap_uwire_s { + target_phys_addr_t base; + qemu_irq txirq; + qemu_irq rxirq; + qemu_irq txdrq; + + uint16_t txbuf; + uint16_t rxbuf; + uint16_t control; + uint16_t setup[5]; + + struct uwire_slave_s *chip[4]; +}; + +static void omap_uwire_transfer_start(struct omap_uwire_s *s) +{ + int chipselect = (s->control >> 10) & 3; /* INDEX */ + struct uwire_slave_s *slave = s->chip[chipselect]; + + if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ + if (s->control & (1 << 12)) /* CS_CMD */ + if (slave && slave->send) + slave->send(slave->opaque, + s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); + s->control &= ~(1 << 14); /* CSRB */ + /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or + * a DRQ. When is the level IRQ supposed to be reset? */ + } + + if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ + if (s->control & (1 << 12)) /* CS_CMD */ + if (slave && slave->receive) + s->rxbuf = slave->receive(slave->opaque); + s->control |= 1 << 15; /* RDRB */ + /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or + * a DRQ. When is the level IRQ supposed to be reset? */ + } +} + +static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* RDR */ + s->control &= ~(1 << 15); /* RDRB */ + return s->rxbuf; + + case 0x04: /* CSR */ + return s->control; + + case 0x08: /* SR1 */ + return s->setup[0]; + case 0x0c: /* SR2 */ + return s->setup[1]; + case 0x10: /* SR3 */ + return s->setup[2]; + case 0x14: /* SR4 */ + return s->setup[3]; + case 0x18: /* SR5 */ + return s->setup[4]; + } + + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_uwire_write(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* TDR */ + s->txbuf = value; /* TD */ + if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ + ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ + (s->control & (1 << 12)))) { /* CS_CMD */ + s->control |= 1 << 14; /* CSRB */ + omap_uwire_transfer_start(s); + } + break; + + case 0x04: /* CSR */ + s->control = value & 0x1fff; + if (value & (1 << 13)) /* START */ + omap_uwire_transfer_start(s); + break; + + case 0x08: /* SR1 */ + s->setup[0] = value & 0x003f; + break; + + case 0x0c: /* SR2 */ + s->setup[1] = value & 0x0fc0; + break; + + case 0x10: /* SR3 */ + s->setup[2] = value & 0x0003; + break; + + case 0x14: /* SR4 */ + s->setup[3] = value & 0x0001; + break; + + case 0x18: /* SR5 */ + s->setup[4] = value & 0x000f; + break; + + default: + OMAP_BAD_REG(addr); + return; + } +} + +static CPUReadMemoryFunc *omap_uwire_readfn[] = { + omap_badwidth_read16, + omap_uwire_read, + omap_badwidth_read16, +}; + +static CPUWriteMemoryFunc *omap_uwire_writefn[] = { + omap_badwidth_write16, + omap_uwire_write, + omap_badwidth_write16, +}; + +static void omap_uwire_reset(struct omap_uwire_s *s) +{ + s->control = 0; + s->setup[0] = 0; + s->setup[1] = 0; + s->setup[2] = 0; + s->setup[3] = 0; + s->setup[4] = 0; +} + +struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base, + qemu_irq *irq, qemu_irq dma, omap_clk clk) +{ + int iomemtype; + struct omap_uwire_s *s = (struct omap_uwire_s *) + qemu_mallocz(sizeof(struct omap_uwire_s)); + + s->base = base; + s->txirq = irq[0]; + s->rxirq = irq[1]; + s->txdrq = dma; + omap_uwire_reset(s); + + iomemtype = cpu_register_io_memory(0, omap_uwire_readfn, + omap_uwire_writefn, s); + cpu_register_physical_memory(s->base, 0x800, iomemtype); + + return s; +} + +void omap_uwire_attach(struct omap_uwire_s *s, + struct uwire_slave_s *slave, int chipselect) +{ + if (chipselect < 0 || chipselect > 3) + cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n", __FUNCTION__, + chipselect); + + s->chip[chipselect] = slave; +} + +/* Pseudonoise Pulse-Width Light Modulator */ +static void omap_pwl_update(struct omap_mpu_state_s *s) +{ + int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0; + + if (output != s->pwl.output) { + s->pwl.output = output; + printf("%s: Backlight now at %i/256\n", __FUNCTION__, output); + } +} + +static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* PWL_LEVEL */ + return s->pwl.level; + case 0x04: /* PWL_CTRL */ + return s->pwl.enable; + } + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_pwl_write(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* PWL_LEVEL */ + s->pwl.level = value; + omap_pwl_update(s); + break; + case 0x04: /* PWL_CTRL */ + s->pwl.enable = value & 1; + omap_pwl_update(s); + break; + default: + OMAP_BAD_REG(addr); + return; + } +} + +static CPUReadMemoryFunc *omap_pwl_readfn[] = { + omap_pwl_read, + omap_badwidth_read8, + omap_badwidth_read8, +}; + +static CPUWriteMemoryFunc *omap_pwl_writefn[] = { + omap_pwl_write, + omap_badwidth_write8, + omap_badwidth_write8, +}; + +static void omap_pwl_reset(struct omap_mpu_state_s *s) +{ + s->pwl.output = 0; + s->pwl.level = 0; + s->pwl.enable = 0; + s->pwl.clk = 1; + omap_pwl_update(s); +} + +static void omap_pwl_clk_update(void *opaque, int line, int on) +{ + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; + + s->pwl.clk = on; + omap_pwl_update(s); +} + +static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, + omap_clk clk) +{ + int iomemtype; + + omap_pwl_reset(s); + + iomemtype = cpu_register_io_memory(0, omap_pwl_readfn, + omap_pwl_writefn, s); + cpu_register_physical_memory(base, 0x800, iomemtype); + + omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); +} + +/* Pulse-Width Tone module */ +static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* FRC */ + return s->pwt.frc; + case 0x04: /* VCR */ + return s->pwt.vrc; + case 0x08: /* GCR */ + return s->pwt.gcr; + } + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_pwt_write(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* FRC */ + s->pwt.frc = value & 0x3f; + break; + case 0x04: /* VRC */ + if ((value ^ s->pwt.vrc) & 1) { + if (value & 1) + printf("%s: %iHz buzz on\n", __FUNCTION__, (int) + /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ + ((omap_clk_getrate(s->pwt.clk) >> 3) / + /* Pre-multiplexer divider */ + ((s->pwt.gcr & 2) ? 1 : 154) / + /* Octave multiplexer */ + (2 << (value & 3)) * + /* 101/107 divider */ + ((value & (1 << 2)) ? 101 : 107) * + /* 49/55 divider */ + ((value & (1 << 3)) ? 49 : 55) * + /* 50/63 divider */ + ((value & (1 << 4)) ? 50 : 63) * + /* 80/127 divider */ + ((value & (1 << 5)) ? 80 : 127) / + (107 * 55 * 63 * 127))); + else + printf("%s: silence!\n", __FUNCTION__); + } + s->pwt.vrc = value & 0x7f; + break; + case 0x08: /* GCR */ + s->pwt.gcr = value & 3; + break; + default: + OMAP_BAD_REG(addr); + return; + } +} + +static CPUReadMemoryFunc *omap_pwt_readfn[] = { + omap_pwt_read, + omap_badwidth_read8, + omap_badwidth_read8, +}; + +static CPUWriteMemoryFunc *omap_pwt_writefn[] = { + omap_pwt_write, + omap_badwidth_write8, + omap_badwidth_write8, +}; + +static void omap_pwt_reset(struct omap_mpu_state_s *s) +{ + s->pwt.frc = 0; + s->pwt.vrc = 0; + s->pwt.gcr = 0; +} + +static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s, + omap_clk clk) +{ + int iomemtype; + + s->pwt.clk = clk; + omap_pwt_reset(s); + + iomemtype = cpu_register_io_memory(0, omap_pwt_readfn, + omap_pwt_writefn, s); + cpu_register_physical_memory(base, 0x800, iomemtype); +} + +/* Real-time Clock module */ +struct omap_rtc_s { + target_phys_addr_t base; + qemu_irq irq; + qemu_irq alarm; + QEMUTimer *clk; + + uint8_t interrupts; + uint8_t status; + int16_t comp_reg; + int running; + int pm_am; + int auto_comp; + int round; + struct tm *(*convert)(const time_t *timep, struct tm *result); + struct tm alarm_tm; + time_t alarm_ti; + + struct tm current_tm; + time_t ti; + uint64_t tick; +}; + +static void omap_rtc_interrupts_update(struct omap_rtc_s *s) +{ + /* s->alarm is level-triggered */ + qemu_set_irq(s->alarm, (s->status >> 6) & 1); +} + +static void omap_rtc_alarm_update(struct omap_rtc_s *s) +{ + s->alarm_ti = mktime(&s->alarm_tm); + if (s->alarm_ti == -1) + printf("%s: conversion failed\n", __FUNCTION__); +} + +static inline uint8_t omap_rtc_bcd(int num) +{ + return ((num / 10) << 4) | (num % 10); +} + +static inline int omap_rtc_bin(uint8_t num) +{ + return (num & 15) + 10 * (num >> 4); +} + +static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + uint8_t i; + + switch (offset) { + case 0x00: /* SECONDS_REG */ + return omap_rtc_bcd(s->current_tm.tm_sec); + + case 0x04: /* MINUTES_REG */ + return omap_rtc_bcd(s->current_tm.tm_min); + + case 0x08: /* HOURS_REG */ + if (s->pm_am) + return ((s->current_tm.tm_hour > 11) << 7) | + omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); + else + return omap_rtc_bcd(s->current_tm.tm_hour); + + case 0x0c: /* DAYS_REG */ + return omap_rtc_bcd(s->current_tm.tm_mday); + + case 0x10: /* MONTHS_REG */ + return omap_rtc_bcd(s->current_tm.tm_mon + 1); + + case 0x14: /* YEARS_REG */ + return omap_rtc_bcd(s->current_tm.tm_year % 100); + + case 0x18: /* WEEK_REG */ + return s->current_tm.tm_wday; + + case 0x20: /* ALARM_SECONDS_REG */ + return omap_rtc_bcd(s->alarm_tm.tm_sec); + + case 0x24: /* ALARM_MINUTES_REG */ + return omap_rtc_bcd(s->alarm_tm.tm_min); + + case 0x28: /* ALARM_HOURS_REG */ + if (s->pm_am) + return ((s->alarm_tm.tm_hour > 11) << 7) | + omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); + else + return omap_rtc_bcd(s->alarm_tm.tm_hour); + + case 0x2c: /* ALARM_DAYS_REG */ + return omap_rtc_bcd(s->alarm_tm.tm_mday); + + case 0x30: /* ALARM_MONTHS_REG */ + return omap_rtc_bcd(s->alarm_tm.tm_mon + 1); + + case 0x34: /* ALARM_YEARS_REG */ + return omap_rtc_bcd(s->alarm_tm.tm_year % 100); + + case 0x40: /* RTC_CTRL_REG */ + return (s->pm_am << 3) | (s->auto_comp << 2) | + (s->round << 1) | s->running; + + case 0x44: /* RTC_STATUS_REG */ + i = s->status; + s->status &= ~0x3d; + return i; + + case 0x48: /* RTC_INTERRUPTS_REG */ + return s->interrupts; + + case 0x4c: /* RTC_COMP_LSB_REG */ + return ((uint16_t) s->comp_reg) & 0xff; + + case 0x50: /* RTC_COMP_MSB_REG */ + return ((uint16_t) s->comp_reg) >> 8; + } + + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_rtc_write(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + struct tm new_tm; + time_t ti[2]; + + switch (offset) { + case 0x00: /* SECONDS_REG */ +#if ALMDEBUG + printf("RTC SEC_REG <-- %02x\n", value); +#endif + s->ti -= s->current_tm.tm_sec; + s->ti += omap_rtc_bin(value); + return; + + case 0x04: /* MINUTES_REG */ +#if ALMDEBUG + printf("RTC MIN_REG <-- %02x\n", value); +#endif + s->ti -= s->current_tm.tm_min * 60; + s->ti += omap_rtc_bin(value) * 60; + return; + + case 0x08: /* HOURS_REG */ +#if ALMDEBUG + printf("RTC HRS_REG <-- %02x\n", value); +#endif + s->ti -= s->current_tm.tm_hour * 3600; + if (s->pm_am) { + s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600; + s->ti += ((value >> 7) & 1) * 43200; + } else + s->ti += omap_rtc_bin(value & 0x3f) * 3600; + return; + + case 0x0c: /* DAYS_REG */ +#if ALMDEBUG + printf("RTC DAY_REG <-- %02x\n", value); +#endif + s->ti -= s->current_tm.tm_mday * 86400; + s->ti += omap_rtc_bin(value) * 86400; + return; + + case 0x10: /* MONTHS_REG */ +#if ALMDEBUG + printf("RTC MTH_REG <-- %02x\n", value); +#endif + memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); + new_tm.tm_mon = omap_rtc_bin(value); + ti[0] = mktime(&s->current_tm); + ti[1] = mktime(&new_tm); + + if (ti[0] != -1 && ti[1] != -1) { + s->ti -= ti[0]; + s->ti += ti[1]; + } else { + /* A less accurate version */ + s->ti -= s->current_tm.tm_mon * 2592000; + s->ti += omap_rtc_bin(value) * 2592000; + } + return; + + case 0x14: /* YEARS_REG */ +#if ALMDEBUG + printf("RTC YRS_REG <-- %02x\n", value); +#endif + memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); + new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100); + ti[0] = mktime(&s->current_tm); + ti[1] = mktime(&new_tm); + + if (ti[0] != -1 && ti[1] != -1) { + s->ti -= ti[0]; + s->ti += ti[1]; + } else { + /* A less accurate version */ + s->ti -= (s->current_tm.tm_year % 100) * 31536000; + s->ti += omap_rtc_bin(value) * 31536000; + } + return; + + case 0x18: /* WEEK_REG */ + return; /* Ignored */ + + case 0x20: /* ALARM_SECONDS_REG */ +#if ALMDEBUG + printf("ALM SEC_REG <-- %02x\n", value); +#endif + s->alarm_tm.tm_sec = omap_rtc_bin(value); + omap_rtc_alarm_update(s); + return; + + case 0x24: /* ALARM_MINUTES_REG */ +#if ALMDEBUG + printf("ALM MIN_REG <-- %02x\n", value); +#endif + s->alarm_tm.tm_min = omap_rtc_bin(value); + omap_rtc_alarm_update(s); + return; + + case 0x28: /* ALARM_HOURS_REG */ +#if ALMDEBUG + printf("ALM HRS_REG <-- %02x\n", value); +#endif + if (s->pm_am) + s->alarm_tm.tm_hour = + ((omap_rtc_bin(value & 0x3f)) % 12) + + ((value >> 7) & 1) * 12; + else + s->alarm_tm.tm_hour = omap_rtc_bin(value); + omap_rtc_alarm_update(s); + return; + + case 0x2c: /* ALARM_DAYS_REG */ +#if ALMDEBUG + printf("ALM DAY_REG <-- %02x\n", value); +#endif + s->alarm_tm.tm_mday = omap_rtc_bin(value); + omap_rtc_alarm_update(s); + return; + + case 0x30: /* ALARM_MONTHS_REG */ +#if ALMDEBUG + printf("ALM MON_REG <-- %02x\n", value); +#endif + s->alarm_tm.tm_mon = omap_rtc_bin(value); + omap_rtc_alarm_update(s); + return; + + case 0x34: /* ALARM_YEARS_REG */ +#if ALMDEBUG + printf("ALM YRS_REG <-- %02x\n", value); +#endif + s->alarm_tm.tm_year = omap_rtc_bin(value); + omap_rtc_alarm_update(s); + return; + + case 0x40: /* RTC_CTRL_REG */ +#if ALMDEBUG + printf("RTC CONTROL <-- %02x\n", value); +#endif + s->pm_am = (value >> 3) & 1; + s->auto_comp = (value >> 2) & 1; + s->round = (value >> 1) & 1; + s->running = value & 1; + s->status &= 0xfd; + s->status |= s->running << 1; + return; + + case 0x44: /* RTC_STATUS_REG */ +#if ALMDEBUG + printf("RTC STATUSL <-- %02x\n", value); +#endif + s->status &= ~((value & 0xc0) ^ 0x80); + omap_rtc_interrupts_update(s); + return; + + case 0x48: /* RTC_INTERRUPTS_REG */ +#if ALMDEBUG + printf("RTC INTRS <-- %02x\n", value); +#endif + s->interrupts = value; + return; + + case 0x4c: /* RTC_COMP_LSB_REG */ +#if ALMDEBUG + printf("RTC COMPLSB <-- %02x\n", value); +#endif + s->comp_reg &= 0xff00; + s->comp_reg |= 0x00ff & value; + return; + + case 0x50: /* RTC_COMP_MSB_REG */ +#if ALMDEBUG + printf("RTC COMPMSB <-- %02x\n", value); +#endif + s->comp_reg &= 0x00ff; + s->comp_reg |= 0xff00 & (value << 8); + return; + + default: + OMAP_BAD_REG(addr); + return; + } +} + +static CPUReadMemoryFunc *omap_rtc_readfn[] = { + omap_rtc_read, + omap_badwidth_read8, + omap_badwidth_read8, +}; + +static CPUWriteMemoryFunc *omap_rtc_writefn[] = { + omap_rtc_write, + omap_badwidth_write8, + omap_badwidth_write8, +}; + +static void omap_rtc_tick(void *opaque) +{ + struct omap_rtc_s *s = opaque; + + if (s->round) { + /* Round to nearest full minute. */ + if (s->current_tm.tm_sec < 30) + s->ti -= s->current_tm.tm_sec; + else + s->ti += 60 - s->current_tm.tm_sec; + + s->round = 0; + } + + localtime_r(&s->ti, &s->current_tm); + + if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { + s->status |= 0x40; + omap_rtc_interrupts_update(s); + } + + if (s->interrupts & 0x04) + switch (s->interrupts & 3) { + case 0: + s->status |= 0x04; + qemu_irq_pulse(s->irq); + break; + case 1: + if (s->current_tm.tm_sec) + break; + s->status |= 0x08; + qemu_irq_pulse(s->irq); + break; + case 2: + if (s->current_tm.tm_sec || s->current_tm.tm_min) + break; + s->status |= 0x10; + qemu_irq_pulse(s->irq); + break; + case 3: + if (s->current_tm.tm_sec || + s->current_tm.tm_min || s->current_tm.tm_hour) + break; + s->status |= 0x20; + qemu_irq_pulse(s->irq); + break; + } + + /* Move on */ + if (s->running) + s->ti ++; + s->tick += 1000; + + /* + * Every full hour add a rough approximation of the compensation + * register to the 32kHz Timer (which drives the RTC) value. + */ + if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) + s->tick += s->comp_reg * 1000 / 32768; + + qemu_mod_timer(s->clk, s->tick); +} + +static void omap_rtc_reset(struct omap_rtc_s *s) +{ + s->interrupts = 0; + s->comp_reg = 0; + s->running = 0; + s->pm_am = 0; + s->auto_comp = 0; + s->round = 0; + s->tick = qemu_get_clock(rt_clock); + memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); + s->alarm_tm.tm_mday = 0x01; + s->status = 1 << 7; + time(&s->ti); + s->ti = mktime(s->convert(&s->ti, &s->current_tm)); + + omap_rtc_alarm_update(s); + omap_rtc_tick(s); +} + +struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, + qemu_irq *irq, omap_clk clk) +{ + int iomemtype; + struct omap_rtc_s *s = (struct omap_rtc_s *) + qemu_mallocz(sizeof(struct omap_rtc_s)); + + s->base = base; + s->irq = irq[0]; + s->alarm = irq[1]; + s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); + s->convert = rtc_utc ? gmtime_r : localtime_r; + + omap_rtc_reset(s); + + iomemtype = cpu_register_io_memory(0, omap_rtc_readfn, + omap_rtc_writefn, s); + cpu_register_physical_memory(s->base, 0x800, iomemtype); + + return s; +} + +/* Multi-channel Buffered Serial Port interfaces */ +struct omap_mcbsp_s { + target_phys_addr_t base; + qemu_irq txirq; + qemu_irq rxirq; + qemu_irq txdrq; + qemu_irq rxdrq; + + uint16_t spcr[2]; + uint16_t rcr[2]; + uint16_t xcr[2]; + uint16_t srgr[2]; + uint16_t mcr[2]; + uint16_t pcr; + uint16_t rcer[8]; + uint16_t xcer[8]; + int tx_rate; + int rx_rate; + int tx_req; + int rx_req; + + struct i2s_codec_s *codec; + QEMUTimer *source_timer; + QEMUTimer *sink_timer; +}; + +static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) +{ + int irq; + + switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ + case 0: + irq = (s->spcr[0] >> 1) & 1; /* RRDY */ + break; + case 3: + irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ + break; + default: + irq = 0; + break; + } + + if (irq) + qemu_irq_pulse(s->rxirq); + + switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ + case 0: + irq = (s->spcr[1] >> 1) & 1; /* XRDY */ + break; + case 3: + irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ + break; + default: + irq = 0; + break; + } + + if (irq) + qemu_irq_pulse(s->txirq); +} + +static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) +{ + if ((s->spcr[0] >> 1) & 1) /* RRDY */ + s->spcr[0] |= 1 << 2; /* RFULL */ + s->spcr[0] |= 1 << 1; /* RRDY */ + qemu_irq_raise(s->rxdrq); + omap_mcbsp_intr_update(s); +} + +static void omap_mcbsp_source_tick(void *opaque) +{ + struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; + static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; + + if (!s->rx_rate) + return; + if (s->rx_req) + printf("%s: Rx FIFO overrun\n", __FUNCTION__); + + s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; + + omap_mcbsp_rx_newdata(s); + qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec); +} + +static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) +{ + if (!s->codec || !s->codec->rts) + omap_mcbsp_source_tick(s); + else if (s->codec->in.len) { + s->rx_req = s->codec->in.len; + omap_mcbsp_rx_newdata(s); + } +} + +static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) +{ + qemu_del_timer(s->source_timer); +} + +static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) +{ + s->spcr[0] &= ~(1 << 1); /* RRDY */ + qemu_irq_lower(s->rxdrq); + omap_mcbsp_intr_update(s); +} + +static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) +{ + s->spcr[1] |= 1 << 1; /* XRDY */ + qemu_irq_raise(s->txdrq); + omap_mcbsp_intr_update(s); +} + +static void omap_mcbsp_sink_tick(void *opaque) +{ + struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; + static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; + + if (!s->tx_rate) + return; + if (s->tx_req) + printf("%s: Tx FIFO underrun\n", __FUNCTION__); + + s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; + + omap_mcbsp_tx_newdata(s); + qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec); +} + +static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) +{ + if (!s->codec || !s->codec->cts) + omap_mcbsp_sink_tick(s); + else if (s->codec->out.size) { + s->tx_req = s->codec->out.size; + omap_mcbsp_tx_newdata(s); + } +} + +static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) +{ + s->spcr[1] &= ~(1 << 1); /* XRDY */ + qemu_irq_lower(s->txdrq); + omap_mcbsp_intr_update(s); + if (s->codec && s->codec->cts) + s->codec->tx_swallow(s->codec->opaque); +} + +static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) +{ + s->tx_req = 0; + omap_mcbsp_tx_done(s); + qemu_del_timer(s->sink_timer); +} + +static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) +{ + int prev_rx_rate, prev_tx_rate; + int rx_rate = 0, tx_rate = 0; + int cpu_rate = 1500000; /* XXX */ + + /* TODO: check CLKSTP bit */ + if (s->spcr[1] & (1 << 6)) { /* GRST */ + if (s->spcr[0] & (1 << 0)) { /* RRST */ + if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ + (s->pcr & (1 << 8))) { /* CLKRM */ + if (~s->pcr & (1 << 7)) /* SCLKME */ + rx_rate = cpu_rate / + ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ + } else + if (s->codec) + rx_rate = s->codec->rx_rate; + } + + if (s->spcr[1] & (1 << 0)) { /* XRST */ + if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ + (s->pcr & (1 << 9))) { /* CLKXM */ + if (~s->pcr & (1 << 7)) /* SCLKME */ + tx_rate = cpu_rate / + ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ + } else + if (s->codec) + tx_rate = s->codec->tx_rate; + } + } + prev_tx_rate = s->tx_rate; + prev_rx_rate = s->rx_rate; + s->tx_rate = tx_rate; + s->rx_rate = rx_rate; + + if (s->codec) + s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); + + if (!prev_tx_rate && tx_rate) + omap_mcbsp_tx_start(s); + else if (s->tx_rate && !tx_rate) + omap_mcbsp_tx_stop(s); + + if (!prev_rx_rate && rx_rate) + omap_mcbsp_rx_start(s); + else if (prev_tx_rate && !tx_rate) + omap_mcbsp_rx_stop(s); +} + +static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + uint16_t ret; + + switch (offset) { + case 0x00: /* DRR2 */ + if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ + return 0x0000; + /* Fall through. */ + case 0x02: /* DRR1 */ + if (s->rx_req < 2) { + printf("%s: Rx FIFO underrun\n", __FUNCTION__); + omap_mcbsp_rx_done(s); + } else { + s->tx_req -= 2; + if (s->codec && s->codec->in.len >= 2) { + ret = s->codec->in.fifo[s->codec->in.start ++] << 8; + ret |= s->codec->in.fifo[s->codec->in.start ++]; + s->codec->in.len -= 2; + } else + ret = 0x0000; + if (!s->tx_req) + omap_mcbsp_rx_done(s); + return ret; + } + return 0x0000; + + case 0x04: /* DXR2 */ + case 0x06: /* DXR1 */ + return 0x0000; + + case 0x08: /* SPCR2 */ + return s->spcr[1]; + case 0x0a: /* SPCR1 */ + return s->spcr[0]; + case 0x0c: /* RCR2 */ + return s->rcr[1]; + case 0x0e: /* RCR1 */ + return s->rcr[0]; + case 0x10: /* XCR2 */ + return s->xcr[1]; + case 0x12: /* XCR1 */ + return s->xcr[0]; + case 0x14: /* SRGR2 */ + return s->srgr[1]; + case 0x16: /* SRGR1 */ + return s->srgr[0]; + case 0x18: /* MCR2 */ + return s->mcr[1]; + case 0x1a: /* MCR1 */ + return s->mcr[0]; + case 0x1c: /* RCERA */ + return s->rcer[0]; + case 0x1e: /* RCERB */ + return s->rcer[1]; + case 0x20: /* XCERA */ + return s->xcer[0]; + case 0x22: /* XCERB */ + return s->xcer[1]; + case 0x24: /* PCR0 */ + return s->pcr; + case 0x26: /* RCERC */ + return s->rcer[2]; + case 0x28: /* RCERD */ + return s->rcer[3]; + case 0x2a: /* XCERC */ + return s->xcer[2]; + case 0x2c: /* XCERD */ + return s->xcer[3]; + case 0x2e: /* RCERE */ + return s->rcer[4]; + case 0x30: /* RCERF */ + return s->rcer[5]; + case 0x32: /* XCERE */ + return s->xcer[4]; + case 0x34: /* XCERF */ + return s->xcer[5]; + case 0x36: /* RCERG */ + return s->rcer[6]; + case 0x38: /* RCERH */ + return s->rcer[7]; + case 0x3a: /* XCERG */ + return s->xcer[6]; + case 0x3c: /* XCERH */ + return s->xcer[7]; + } + + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* DRR2 */ + case 0x02: /* DRR1 */ + OMAP_RO_REG(addr); + return; + + case 0x04: /* DXR2 */ + if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ + return; + /* Fall through. */ + case 0x06: /* DXR1 */ + if (s->tx_req > 1) { + s->tx_req -= 2; + if (s->codec && s->codec->cts) { + s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; + s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; + } + if (s->tx_req < 2) + omap_mcbsp_tx_done(s); + } else + printf("%s: Tx FIFO overrun\n", __FUNCTION__); + return; + + case 0x08: /* SPCR2 */ + s->spcr[1] &= 0x0002; + s->spcr[1] |= 0x03f9 & value; + s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ + if (~value & 1) /* XRST */ + s->spcr[1] &= ~6; + omap_mcbsp_req_update(s); + return; + case 0x0a: /* SPCR1 */ + s->spcr[0] &= 0x0006; + s->spcr[0] |= 0xf8f9 & value; + if (value & (1 << 15)) /* DLB */ + printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__); + if (~value & 1) { /* RRST */ + s->spcr[0] &= ~6; + s->rx_req = 0; + omap_mcbsp_rx_done(s); + } + omap_mcbsp_req_update(s); + return; + + case 0x0c: /* RCR2 */ + s->rcr[1] = value & 0xffff; + return; + case 0x0e: /* RCR1 */ + s->rcr[0] = value & 0x7fe0; + return; + case 0x10: /* XCR2 */ + s->xcr[1] = value & 0xffff; + return; + case 0x12: /* XCR1 */ + s->xcr[0] = value & 0x7fe0; + return; + case 0x14: /* SRGR2 */ + s->srgr[1] = value & 0xffff; + omap_mcbsp_req_update(s); + return; + case 0x16: /* SRGR1 */ + s->srgr[0] = value & 0xffff; + omap_mcbsp_req_update(s); + return; + case 0x18: /* MCR2 */ + s->mcr[1] = value & 0x03e3; + if (value & 3) /* XMCM */ + printf("%s: Tx channel selection mode enable attempt\n", + __FUNCTION__); + return; + case 0x1a: /* MCR1 */ + s->mcr[0] = value & 0x03e1; + if (value & 1) /* RMCM */ + printf("%s: Rx channel selection mode enable attempt\n", + __FUNCTION__); + return; + case 0x1c: /* RCERA */ + s->rcer[0] = value & 0xffff; + return; + case 0x1e: /* RCERB */ + s->rcer[1] = value & 0xffff; + return; + case 0x20: /* XCERA */ + s->xcer[0] = value & 0xffff; + return; + case 0x22: /* XCERB */ + s->xcer[1] = value & 0xffff; + return; + case 0x24: /* PCR0 */ + s->pcr = value & 0x7faf; + return; + case 0x26: /* RCERC */ + s->rcer[2] = value & 0xffff; + return; + case 0x28: /* RCERD */ + s->rcer[3] = value & 0xffff; + return; + case 0x2a: /* XCERC */ + s->xcer[2] = value & 0xffff; + return; + case 0x2c: /* XCERD */ + s->xcer[3] = value & 0xffff; + return; + case 0x2e: /* RCERE */ + s->rcer[4] = value & 0xffff; + return; + case 0x30: /* RCERF */ + s->rcer[5] = value & 0xffff; + return; + case 0x32: /* XCERE */ + s->xcer[4] = value & 0xffff; + return; + case 0x34: /* XCERF */ + s->xcer[5] = value & 0xffff; + return; + case 0x36: /* RCERG */ + s->rcer[6] = value & 0xffff; + return; + case 0x38: /* RCERH */ + s->rcer[7] = value & 0xffff; + return; + case 0x3a: /* XCERG */ + s->xcer[6] = value & 0xffff; + return; + case 0x3c: /* XCERH */ + s->xcer[7] = value & 0xffff; + return; + } + + OMAP_BAD_REG(addr); +} + +static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + if (offset == 0x04) { /* DXR */ + if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ + return; + if (s->tx_req > 3) { + s->tx_req -= 4; + if (s->codec && s->codec->cts) { + s->codec->out.fifo[s->codec->out.len ++] = + (value >> 24) & 0xff; + s->codec->out.fifo[s->codec->out.len ++] = + (value >> 16) & 0xff; + s->codec->out.fifo[s->codec->out.len ++] = + (value >> 8) & 0xff; + s->codec->out.fifo[s->codec->out.len ++] = + (value >> 0) & 0xff; + } + if (s->tx_req < 4) + omap_mcbsp_tx_done(s); + } else + printf("%s: Tx FIFO overrun\n", __FUNCTION__); + return; + } + + omap_badwidth_write16(opaque, addr, value); +} + +static CPUReadMemoryFunc *omap_mcbsp_readfn[] = { + omap_badwidth_read16, + omap_mcbsp_read, + omap_badwidth_read16, +}; + +static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = { + omap_badwidth_write16, + omap_mcbsp_writeh, + omap_mcbsp_writew, +}; + +static void omap_mcbsp_reset(struct omap_mcbsp_s *s) +{ + memset(&s->spcr, 0, sizeof(s->spcr)); + memset(&s->rcr, 0, sizeof(s->rcr)); + memset(&s->xcr, 0, sizeof(s->xcr)); + s->srgr[0] = 0x0001; + s->srgr[1] = 0x2000; + memset(&s->mcr, 0, sizeof(s->mcr)); + memset(&s->pcr, 0, sizeof(s->pcr)); + memset(&s->rcer, 0, sizeof(s->rcer)); + memset(&s->xcer, 0, sizeof(s->xcer)); + s->tx_req = 0; + s->rx_req = 0; + s->tx_rate = 0; + s->rx_rate = 0; + qemu_del_timer(s->source_timer); + qemu_del_timer(s->sink_timer); +} + +struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base, + qemu_irq *irq, qemu_irq *dma, omap_clk clk) +{ + int iomemtype; + struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) + qemu_mallocz(sizeof(struct omap_mcbsp_s)); + + s->base = base; + s->txirq = irq[0]; + s->rxirq = irq[1]; + s->txdrq = dma[0]; + s->rxdrq = dma[1]; + s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s); + s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s); + omap_mcbsp_reset(s); + + iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn, + omap_mcbsp_writefn, s); + cpu_register_physical_memory(s->base, 0x800, iomemtype); + + return s; +} + +static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) +{ + struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; + + if (s->rx_rate) { + s->rx_req = s->codec->in.len; + omap_mcbsp_rx_newdata(s); + } +} + +static void omap_mcbsp_i2s_start(void *opaque, int line, int level) +{ + struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; + + if (s->tx_rate) { + s->tx_req = s->codec->out.size; + omap_mcbsp_tx_newdata(s); + } +} + +void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave) +{ + s->codec = slave; + slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0]; + slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0]; +} + +/* LED Pulse Generators */ +struct omap_lpg_s { + target_phys_addr_t base; + QEMUTimer *tm; + + uint8_t control; + uint8_t power; + int64_t on; + int64_t period; + int clk; + int cycle; +}; + +static void omap_lpg_tick(void *opaque) +{ + struct omap_lpg_s *s = opaque; + + if (s->cycle) + qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on); + else + qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on); + + s->cycle = !s->cycle; + printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); +} + +static void omap_lpg_update(struct omap_lpg_s *s) +{ + int64_t on, period = 1, ticks = 1000; + static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; + + if (~s->control & (1 << 6)) /* LPGRES */ + on = 0; + else if (s->control & (1 << 7)) /* PERM_ON */ + on = period; + else { + period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ + 256 / 32); + on = (s->clk && s->power) ? muldiv64(ticks, + per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ + } + + qemu_del_timer(s->tm); + if (on == period && s->on < s->period) + printf("%s: LED is on\n", __FUNCTION__); + else if (on == 0 && s->on) + printf("%s: LED is off\n", __FUNCTION__); + else if (on && (on != s->on || period != s->period)) { + s->cycle = 0; + s->on = on; + s->period = period; + omap_lpg_tick(s); + return; + } + + s->on = on; + s->period = period; +} + +static void omap_lpg_reset(struct omap_lpg_s *s) +{ + s->control = 0x00; + s->power = 0x00; + s->clk = 1; + omap_lpg_update(s); +} + +static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* LCR */ + return s->control; + + case 0x04: /* PMR */ + return s->power; + } + + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_lpg_write(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; + int offset = addr & OMAP_MPUI_REG_MASK; + + switch (offset) { + case 0x00: /* LCR */ + if (~value & (1 << 6)) /* LPGRES */ + omap_lpg_reset(s); + s->control = value & 0xff; + omap_lpg_update(s); + return; + + case 0x04: /* PMR */ + s->power = value & 0x01; + omap_lpg_update(s); + return; + + default: + OMAP_BAD_REG(addr); + return; + } +} + +static CPUReadMemoryFunc *omap_lpg_readfn[] = { + omap_lpg_read, + omap_badwidth_read8, + omap_badwidth_read8, +}; + +static CPUWriteMemoryFunc *omap_lpg_writefn[] = { + omap_lpg_write, + omap_badwidth_write8, + omap_badwidth_write8, +}; + +static void omap_lpg_clk_update(void *opaque, int line, int on) +{ + struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; + + s->clk = on; + omap_lpg_update(s); +} + +struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk) +{ + int iomemtype; + struct omap_lpg_s *s = (struct omap_lpg_s *) + qemu_mallocz(sizeof(struct omap_lpg_s)); + + s->base = base; + s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s); + + omap_lpg_reset(s); + + iomemtype = cpu_register_io_memory(0, omap_lpg_readfn, + omap_lpg_writefn, s); + cpu_register_physical_memory(s->base, 0x800, iomemtype); + + omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); + + return s; +} + +/* MPUI Peripheral Bridge configuration */ +static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr) +{ + if (addr == OMAP_MPUI_BASE) /* CMR */ + return 0xfe4d; + + OMAP_BAD_REG(addr); + return 0; +} + +static CPUReadMemoryFunc *omap_mpui_io_readfn[] = { + omap_badwidth_read16, + omap_mpui_io_read, + omap_badwidth_read16, +}; + +static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = { + omap_badwidth_write16, + omap_badwidth_write16, + omap_badwidth_write16, +}; + +static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu) +{ + int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn, + omap_mpui_io_writefn, mpu); + cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype); +} + /* General chip reset */ static void omap_mpu_reset(void *opaque) { struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; - omap_clkm_reset(mpu); omap_inth_reset(mpu->ih[0]); omap_inth_reset(mpu->ih[1]); omap_dma_reset(mpu->dma); @@ -2810,34 +5507,124 @@ static void omap_mpu_reset(void *opaque) omap_dpll_reset(&mpu->dpll[0]); omap_dpll_reset(&mpu->dpll[1]); omap_dpll_reset(&mpu->dpll[2]); - omap_uart_reset(mpu->uart1); - omap_uart_reset(mpu->uart2); - omap_uart_reset(mpu->uart3); + omap_uart_reset(mpu->uart[0]); + omap_uart_reset(mpu->uart[1]); + omap_uart_reset(mpu->uart[2]); omap_mmc_reset(mpu->mmc); + omap_mpuio_reset(mpu->mpuio); + omap_gpio_reset(mpu->gpio); + omap_uwire_reset(mpu->microwire); + omap_pwl_reset(mpu); + omap_pwt_reset(mpu); + omap_i2c_reset(mpu->i2c); + omap_rtc_reset(mpu->rtc); + omap_mcbsp_reset(mpu->mcbsp1); + omap_mcbsp_reset(mpu->mcbsp2); + omap_mcbsp_reset(mpu->mcbsp3); + omap_lpg_reset(mpu->led[0]); + omap_lpg_reset(mpu->led[1]); + omap_clkm_reset(mpu); cpu_reset(mpu->env); } +static const struct omap_map_s { + target_phys_addr_t phys_dsp; + target_phys_addr_t phys_mpu; + uint32_t size; + const char *name; +} omap15xx_dsp_mm[] = { + /* Strobe 0 */ + { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ + { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ + { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ + { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ + { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ + { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ + { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ + { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ + { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ + { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ + { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ + { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ + { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ + { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ + { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ + { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ + { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ + /* Strobe 1 */ + { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ + + { 0 } +}; + +static void omap_setup_dsp_mapping(const struct omap_map_s *map) +{ + int io; + + for (; map->phys_dsp; map ++) { + io = cpu_get_physical_page_desc(map->phys_mpu); + + cpu_register_physical_memory(map->phys_dsp, map->size, io); + } +} + static void omap_mpu_wakeup(void *opaque, int irq, int req) { struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; - cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); + if (mpu->env->halted) + cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); } +struct dma_irq_map { + int ih; + int intr; +}; + +static const struct dma_irq_map omap_dma_irq_map[] = { + { 0, OMAP_INT_DMA_CH0_6 }, + { 0, OMAP_INT_DMA_CH1_7 }, + { 0, OMAP_INT_DMA_CH2_8 }, + { 0, OMAP_INT_DMA_CH3 }, + { 0, OMAP_INT_DMA_CH4 }, + { 0, OMAP_INT_DMA_CH5 }, + { 1, OMAP_INT_1610_DMA_CH6 }, + { 1, OMAP_INT_1610_DMA_CH7 }, + { 1, OMAP_INT_1610_DMA_CH8 }, + { 1, OMAP_INT_1610_DMA_CH9 }, + { 1, OMAP_INT_1610_DMA_CH10 }, + { 1, OMAP_INT_1610_DMA_CH11 }, + { 1, OMAP_INT_1610_DMA_CH12 }, + { 1, OMAP_INT_1610_DMA_CH13 }, + { 1, OMAP_INT_1610_DMA_CH14 }, + { 1, OMAP_INT_1610_DMA_CH15 } +}; + struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, DisplayState *ds, const char *core) { + int i; struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) qemu_mallocz(sizeof(struct omap_mpu_state_s)); ram_addr_t imif_base, emiff_base; + qemu_irq *cpu_irq; + qemu_irq dma_irqs[6]; + int sdindex; + + if (!core) + core = "ti925t"; /* Core */ s->mpu_model = omap310; - s->env = cpu_init(); + s->env = cpu_init(core); + if (!s->env) { + fprintf(stderr, "Unable to find CPU definition\n"); + exit(1); + } s->sdram_size = sdram_size; s->sram_size = OMAP15XX_SRAM_SIZE; - cpu_arm_set_model(s->env, core ?: "ti925t"); + s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; /* Clocks */ omap_clk_init(s); @@ -2850,17 +5637,21 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, omap_clkm_init(0xfffece00, 0xe1008000, s); - s->ih[0] = omap_inth_init(0xfffecb00, 0x100, - arm_pic_init_cpu(s->env), + cpu_irq = arm_pic_init_cpu(s->env); + s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, + cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], omap_findclk(s, "arminth_ck")); - s->ih[1] = omap_inth_init(0xfffe0000, 0x800, - &s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], + s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, + s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL, omap_findclk(s, "arminth_ck")); s->irq[0] = s->ih[0]->pins; s->irq[1] = s->ih[1]->pins; - s->dma = omap_dma_init(0xfffed800, s->irq[0], s, - omap_findclk(s, "dma_ck")); + for (i = 0; i < 6; i ++) + dma_irqs[i] = s->irq[omap_dma_irq_map[i].ih][omap_dma_irq_map[i].intr]; + s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD], + s, omap_findclk(s, "dma_ck"), omap_dma_3_1); + s->port[emiff ].addr_valid = omap_validate_emiff_addr; s->port[emifs ].addr_valid = omap_validate_emifs_addr; s->port[imif ].addr_valid = omap_validate_imif_addr; @@ -2905,13 +5696,13 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, omap_tcmi_init(0xfffecc00, s); - s->uart1 = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], + s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], omap_findclk(s, "uart1_ck"), serial_hds[0]); - s->uart2 = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], + s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], omap_findclk(s, "uart2_ck"), serial_hds[0] ? serial_hds[1] : 0); - s->uart3 = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3], + s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3], omap_findclk(s, "uart3_ck"), serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); @@ -2919,11 +5710,63 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); - s->mmc = omap_mmc_init(0xfffb7800, s->irq[1][OMAP_INT_OQN], - &s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck")); + sdindex = drive_get_index(IF_SD, 0, 0); + if (sdindex == -1) { + fprintf(stderr, "qemu: missing SecureDigital device\n"); + exit(1); + } + s->mmc = omap_mmc_init(0xfffb7800, drives_table[sdindex].bdrv, + s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX], + omap_findclk(s, "mmc_ck")); + + s->mpuio = omap_mpuio_init(0xfffb5000, + s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO], + s->wakeup, omap_findclk(s, "clk32-kHz")); + + s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1], + omap_findclk(s, "arm_gpio_ck")); + + s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX], + s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); + + omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck")); + omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck")); + + s->i2c = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C], + &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck")); + + s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER], + omap_findclk(s, "clk32-kHz")); + + s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX], + &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); + s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX], + &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); + s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX], + &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); + + s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz")); + s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz")); + + /* Register mappings not currenlty implemented: + * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) + * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) + * USB W2FC fffb4000 - fffb47ff + * Camera Interface fffb6800 - fffb6fff + * USB Host fffba000 - fffba7ff + * FAC fffba800 - fffbafff + * HDQ/1-Wire fffbc000 - fffbc7ff + * TIPB switches fffbc800 - fffbcfff + * Mailbox fffcf000 - fffcf7ff + * Local bus IF fffec100 - fffec1ff + * Local bus MMU fffec200 - fffec2ff + * DSP MMU fffed200 - fffed2ff + */ + + omap_setup_dsp_mapping(omap15xx_dsp_mm); + omap_setup_mpui_io(s); qemu_register_reset(omap_mpu_reset, s); - s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; return s; } |