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| author |   Marcelo Tosatti <mtosatti@redhat.com> | 2012-10-11 05:00:35 -0300 |
|---|---|---|
| committer | Marcelo Tosatti <mtosatti@redhat.com> | 2012-10-11 05:00:35 -0300 |
| commit | 6b852ae04e3aa1adfeac5a62d6ab71870bcc7c5d (patch) | |
| tree | cdf94fdf09a6b4abecff647784d82bc1ad1758c5 /tcg/mips/tcg-target.h | |
| parent | 8ed1d2756d3347c2b021748d8c272ff650f57dd0 (diff) | |
| parent | f430694188293f99a316bfa375b7cc17d23a06ed (diff) | |
Merge commit 'f430694188293f99a316bfa375b7cc17d23a06ed' into upstream-merge
* commit 'f430694188293f99a316bfa375b7cc17d23a06ed': (248 commits)
add pc-1.3 machine type
Cleanup unused global var qemu_system_powerdown
target-sparc: use notifier for signaling guest system_powerdown command
target-arm: use notifier for signaling guest system_powerdown command
acpi: use notifier for signaling guest system_powerdown command
Introduce powerdown_notifiers
tcg/i386: fix build with -march < i686
tcg: Streamline movcond_i64 using movcond_i32
tcg: Streamline movcond_i64 using 32-bit arithmetic
tcg: Sanity check goto_tb input
tcg: Sanity check deposit inputs
tcg: Add tcg_debug_assert
tcg: Implement concat*_i64 with deposit_i64
tcg: Emit XORI as NOT for appropriate constants
tcg: Optimize initial inputs for ori_i64
tcg: Emit ANDI as EXTU for appropriate constants
tcg: Adjust descriptions of *cond opcodes
tcg/mips: fix MIPS32(R2) detection
block: remove keep_read_only flag from BlockDriverState struct
block: convert bdrv_commit() to use bdrv_reopen()
...
Conflicts:
hw/pc_piix.c
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'tcg/mips/tcg-target.h')
| -rw-r--r-- | tcg/mips/tcg-target.h | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 1c6193180..7020d6584 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -80,16 +80,34 @@ typedef enum { #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_nor_i32 1 -#define TCG_TARGET_HAS_rot_i32 0 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 -#define TCG_TARGET_HAS_bswap32_i32 0 -#define TCG_TARGET_HAS_bswap16_i32 0 #define TCG_TARGET_HAS_andc_i32 0 #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 + +/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */ +#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ + defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \ + defined(_MIPS_ARCH_MIPS4) +#define TCG_TARGET_HAS_movcond_i32 1 +#else +#define TCG_TARGET_HAS_movcond_i32 0 +#endif + +/* optional instructions only implemented on MIPS32R2 */ +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) +#define TCG_TARGET_HAS_bswap16_i32 1 +#define TCG_TARGET_HAS_bswap32_i32 1 +#define TCG_TARGET_HAS_rot_i32 1 +#define TCG_TARGET_HAS_deposit_i32 1 +#else +#define TCG_TARGET_HAS_bswap16_i32 0 +#define TCG_TARGET_HAS_bswap32_i32 0 +#define TCG_TARGET_HAS_rot_i32 0 #define TCG_TARGET_HAS_deposit_i32 0 +#endif /* optional instructions automatically implemented */ #define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */ |