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authorAvi Kivity <avi@redhat.com>2012-09-09 16:21:39 +0300
committerAvi Kivity <avi@redhat.com>2012-09-09 16:21:39 +0300
commit3505aa6bec1a3bb474d81c495515b44654659a38 (patch)
treebf0f5f9e1a76159752047cdb239c62cbbd1f2ace /hw/pc.c
parent7fa12eb15f95c269f488fce4096093c96dbaffab (diff)
parent4ce5bc2dd1914a706725186c6563e8f92eedfc84 (diff)
Merge tag 'v1.1.2' into stable-1.1qemu-kvm-1.1.2stable-1.1
* tag 'v1.1.2': (74 commits) update VERSION for 1.1.2 console: bounds check whenever changing the cursor due to an escape code qemu-timer: properly arm alarm timer for timers set by device initialization target-xtensa: return ENOSYS for unimplemented simcalls target-xtensa: fix big-endian BBS/BBC implementation ehci: Fix NULL ptr deref when unplugging an USB dev with an iso stream active msix: make [un]use vectors on reset/load optional reset PMBA and PMREGMISC PIIX4 registers. qemu_rearm_alarm_timer: do not call rearm if the next deadline is INT64_MAX qemu-ga: Fix null pointer passed to unlink in failure branch memory: Fix copy&paste mistake in memory_region_iorange_write ivshmem: remove redundant ioeventfd configuration hw/arm_gic.c: Define .class_size in arm_gic_info TypeInfo tcg/mips: fix broken CONFIG_TCG_PASS_AREG0 code audio/winwave: previous audio buffer should be flushed target-mips: allow microMIPS SWP and SDP to have RD equal to BASE target-mips: add privilege level check to several Cop0 instructions mips-linux-user: Always support rdhwr. target-mips: Streamline indexed cp1 memory addressing. Fix order of CVT.PS.S operands ... Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'hw/pc.c')
-rw-r--r--hw/pc.c31
1 files changed, 18 insertions, 13 deletions
diff --git a/hw/pc.c b/hw/pc.c
index dc3193379..77bd05ec5 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -344,32 +344,37 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
/* various important CMOS locations needed by PC/Bochs bios */
/* memory size */
- val = 640; /* base memory in K */
+ /* base memory (first MiB) */
+ val = MIN(ram_size / 1024, 640);
rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val >> 8);
-
- val = (ram_size / 1024) - 1024;
+ /* extended memory (next 64MiB) */
+ if (ram_size > 1024 * 1024) {
+ val = (ram_size - 1024 * 1024) / 1024;
+ } else {
+ val = 0;
+ }
if (val > 65535)
val = 65535;
rtc_set_memory(s, 0x17, val);
rtc_set_memory(s, 0x18, val >> 8);
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
-
- if (above_4g_mem_size) {
- rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
- rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
- rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
- }
-
- if (ram_size > (16 * 1024 * 1024))
- val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
- else
+ /* memory between 16MiB and 4GiB */
+ if (ram_size > 16 * 1024 * 1024) {
+ val = (ram_size - 16 * 1024 * 1024) / 65536;
+ } else {
val = 0;
+ }
if (val > 65535)
val = 65535;
rtc_set_memory(s, 0x34, val);
rtc_set_memory(s, 0x35, val >> 8);
+ /* memory above 4GiB */
+ val = above_4g_mem_size / 65536;
+ rtc_set_memory(s, 0x5b, val);
+ rtc_set_memory(s, 0x5c, val >> 8);
+ rtc_set_memory(s, 0x5d, val >> 16);
/* set the number of CPU */
rtc_set_memory(s, 0x5f, smp_cpus - 1);