diff options
| author |   Richard Henderson <rth@twiddle.net> | 2012-03-30 13:16:36 -0400 |
|---|---|---|
| committer |   Michael Roth <mdroth@linux.vnet.ibm.com> | 2012-08-28 01:50:03 -0500 |
| commit | 2f0f684cce95a9e0ef709cc2614fd1512cf0bb85 (patch) | |
| tree | cf6885f19dc2fe1ab57ba9409db99ac2f139100d | |
| parent | bc4321e754e8fadac0d8173c73719700a8c98d4a (diff) | |
target-mips: Streamline indexed cp1 memory addressing.
We've already eliminated both base and index being zero.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit 05168674505153a641c7bfddb691d2eda11d13d1)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
| -rw-r--r-- | target-mips/translate.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 7687566e8..cb6077d80 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, } else if (index == 0) { gen_load_gpr(t0, base); } else { - gen_load_gpr(t0, index); - gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ |