From 2f0f684cce95a9e0ef709cc2614fd1512cf0bb85 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 30 Mar 2012 13:16:36 -0400 Subject: target-mips: Streamline indexed cp1 memory addressing. We've already eliminated both base and index being zero. Signed-off-by: Aurelien Jarno (cherry picked from commit 05168674505153a641c7bfddb691d2eda11d13d1) Signed-off-by: Michael Roth --- target-mips/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 7687566e8..cb6077d80 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, } else if (index == 0) { gen_load_gpr(t0, base); } else { - gen_load_gpr(t0, index); - gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ -- cgit v1.2.3