From c98d174c24b915e9908785feb63eb3b5abe33818 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 14 Mar 2012 12:26:10 +0000 Subject: target-arm: Clear IT bits when taking exceptions in v7M When taking an exception for an M profile core, we must clear the IT bits. Since the IT bits are cached in env->condexec_bits we must clear them there: writing the bits in env->uncached_cpsr has no effect. (Reported as LP:944645.) Signed-off-by: Peter Maydell --- target-arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4116feebf..1314f23d5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -877,7 +877,8 @@ static void do_interrupt_v7m(CPUARMState *env) v7m_push(env, env->regs[1]); v7m_push(env, env->regs[0]); switch_v7m_sp(env, 0); - env->uncached_cpsr &= ~CPSR_IT; + /* Clear IT bits */ + env->condexec_bits = 0; env->regs[14] = lr; addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4); env->regs[15] = addr & 0xfffffffe; -- cgit v1.2.3