From 8f06bf693dec29642255adcc2828bc6b7daa83d9 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sat, 22 Sep 2012 23:08:38 +0200 Subject: tcg/mips: fix MIPS32(R2) detection Fix the MIPS32(R2) cpu detection so that it also works with -march=octeon. Thanks to Andrew Pinski for the hint. Cc: Andrew Pinski Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 10 +++++----- tcg/mips/tcg-target.h | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index f70910a90..34e3e7f82 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -419,7 +419,7 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type, static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); #else /* ret and arg can't be register at */ @@ -436,7 +436,7 @@ static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); #else @@ -454,7 +454,7 @@ static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); #else @@ -480,7 +480,7 @@ static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); #else tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); @@ -490,7 +490,7 @@ static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); #else tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d147e70eb..7020d6584 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -88,16 +88,16 @@ typedef enum { #define TCG_TARGET_HAS_nand_i32 0 /* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */ -#if defined(_MIPS_ARCH_MIPS4) || defined(_MIPS_ARCH_MIPS32) || \ - defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_LOONGSON2E) || \ - defined(_MIPS_ARCH_LOONGSON2F) +#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ + defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \ + defined(_MIPS_ARCH_MIPS4) #define TCG_TARGET_HAS_movcond_i32 1 #else #define TCG_TARGET_HAS_movcond_i32 0 #endif /* optional instructions only implemented on MIPS32R2 */ -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_rot_i32 1 -- cgit v1.2.3