From 5ea33884f642ab74a321527d7a91001d1562d671 Mon Sep 17 00:00:00 2001 From: Meador Inge Date: Tue, 21 Aug 2012 12:31:37 -0500 Subject: target-mips: Enable access to required RDHWR hardware registers While running in the usermode emulator all of the required* MIPS32r2 RDHWR hardware registers should be accessible (the Linux kernel enables access to these same registers). Note that these registers are still enabled when the MIPS ISA is not release 2. This is OK since the Linux kernel emulates access to them when they are not available in hardware. * There is also the ULR register which is only recommended for full release 2 compliance. Incidentally, accessing this register in the current implementation works fine without flipping its access bit. Signed-off-by: Meador Inge Signed-off-by: Aurelien Jarno (cherry picked from commit 94159135cb59684853dcd45ff70d6dbc54a29209) Signed-off-by: Michael Roth --- target-mips/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 0c563eedf..7dd21f4f7 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12767,8 +12767,9 @@ void cpu_state_reset(CPUMIPSState *env) #if defined(CONFIG_USER_ONLY) env->hflags = MIPS_HFLAG_UM; - /* Enable access to the SYNCI_Step register. */ - env->CP0_HWREna |= (1 << 1); + /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR + hardware registers. */ + env->CP0_HWREna |= 0x0000000F; if (env->CP0_Config1 & (1 << CP0C1_FP)) { env->hflags |= MIPS_HFLAG_FPU; } -- cgit v1.2.3