diff options
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 104 |
1 files changed, 52 insertions, 52 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 280bfca62..2709010f4 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -111,20 +111,20 @@ void arm_translate_init(void) for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[i]), + offsetof(CPUARMState, regs[i]), regnames[i]); } cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, exclusive_addr), "exclusive_addr"); + offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, exclusive_val), "exclusive_val"); + offsetof(CPUARMState, exclusive_val), "exclusive_val"); cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, exclusive_high), "exclusive_high"); + offsetof(CPUARMState, exclusive_high), "exclusive_high"); #ifdef CONFIG_USER_ONLY cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, exclusive_test), "exclusive_test"); + offsetof(CPUARMState, exclusive_test), "exclusive_test"); cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, exclusive_info), "exclusive_info"); + offsetof(CPUARMState, exclusive_info), "exclusive_info"); #endif #define GEN_HELPER 2 @@ -138,7 +138,7 @@ static inline TCGv load_cpu_offset(int offset) return tmp; } -#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name)) +#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) static inline void store_cpu_offset(TCGv var, int offset) { @@ -147,7 +147,7 @@ static inline void store_cpu_offset(TCGv var, int offset) } #define store_cpu_field(var, name) \ - store_cpu_offset(var, offsetof(CPUState, name)) + store_cpu_offset(var, offsetof(CPUARMState, name)) /* Set a variable to the value of a CPU register. */ static void load_reg_var(DisasContext *s, TCGv var, int reg) @@ -368,7 +368,7 @@ static void gen_add16(TCGv t0, TCGv t1) tcg_temp_free_i32(t1); } -#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF)) +#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, CF)) /* Set CF to the top bit of var. */ static void gen_set_CF_bit31(TCGv var) @@ -382,8 +382,8 @@ static void gen_set_CF_bit31(TCGv var) /* Set N and Z flags from var. */ static inline void gen_logic_CC(TCGv var) { - tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF)); - tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF)); + tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, NF)); + tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, ZF)); } /* T0 += T1 + CF. */ @@ -523,13 +523,13 @@ static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b) #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) case 1: tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); + tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); PAS_OP(s) tcg_temp_free_ptr(tmp); break; case 5: tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); + tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); PAS_OP(u) tcg_temp_free_ptr(tmp); break; @@ -570,13 +570,13 @@ static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b) #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) case 0: tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); + tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); PAS_OP(s) tcg_temp_free_ptr(tmp); break; case 4: tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); + tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); PAS_OP(u) tcg_temp_free_ptr(tmp); break; @@ -725,7 +725,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr) if (s->thumb != (addr & 1)) { tmp = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, addr & 1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb)); + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb)); tcg_temp_free_i32(tmp); } tcg_gen_movi_i32(cpu_R[15], addr & ~1); @@ -743,7 +743,7 @@ static inline void gen_bx(DisasContext *s, TCGv var) /* Variant of store_reg which uses branch&exchange logic when storing to r15 in ARM architecture v7 and above. The source must be a temporary and will be marked as dead. */ -static inline void store_reg_bx(CPUState *env, DisasContext *s, +static inline void store_reg_bx(CPUARMState *env, DisasContext *s, int reg, TCGv var) { if (reg == 15 && ENABLE_ARCH_7) { @@ -757,7 +757,7 @@ static inline void store_reg_bx(CPUState *env, DisasContext *s, * to r15 in ARM architecture v5T and above. This is used for storing * the results of a LDR/LDM/POP into r15, and corresponds to the cases * in the ARM ARM which use the LoadWritePC() pseudocode function. */ -static inline void store_reg_from_load(CPUState *env, DisasContext *s, +static inline void store_reg_from_load(CPUARMState *env, DisasContext *s, int reg, TCGv var) { if (reg == 15 && ENABLE_ARCH_5) { @@ -897,9 +897,9 @@ static TCGv_ptr get_fpstatus_ptr(int neon) TCGv_ptr statusptr = tcg_temp_new_ptr(); int offset; if (neon) { - offset = offsetof(CPUState, vfp.standard_fp_status); + offset = offsetof(CPUARMState, vfp.standard_fp_status); } else { - offset = offsetof(CPUState, vfp.fp_status); + offset = offsetof(CPUARMState, vfp.fp_status); } tcg_gen_addi_ptr(statusptr, cpu_env, offset); return statusptr; @@ -1147,24 +1147,24 @@ static inline void gen_mov_vreg_F0(int dp, int reg) static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) { - tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); + tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); } static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) { - tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); + tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); } static inline TCGv iwmmxt_load_creg(int reg) { TCGv var = tcg_temp_new_i32(); - tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); + tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); return var; } static inline void iwmmxt_store_creg(int reg, TCGv var) { - tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); + tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); tcg_temp_free_i32(var); } @@ -1366,7 +1366,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest) /* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred (ie. an undefined instruction). */ -static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) +static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn) { int rd, wrd; int rdhi, rdlo, rd0, rd1, i; @@ -2370,7 +2370,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) /* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred (ie. an undefined instruction). */ -static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn) +static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn) { int acc, rd0, rd1, rdhi, rdlo; TCGv tmp, tmp2; @@ -2440,7 +2440,7 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn) /* Disassemble system coprocessor instruction. Return nonzero if instruction is not defined. */ -static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn) +static int disas_cp_insn(CPUARMState *env, DisasContext *s, uint32_t insn) { TCGv tmp, tmp2; uint32_t rd = (insn >> 12) & 0xf; @@ -2471,7 +2471,7 @@ static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn) return 0; } -static int cp15_user_ok(CPUState *env, uint32_t insn) +static int cp15_user_ok(CPUARMState *env, uint32_t insn) { int cpn = (insn >> 16) & 0xf; int cpm = insn & 0xf; @@ -2501,7 +2501,7 @@ static int cp15_user_ok(CPUState *env, uint32_t insn) return 0; } -static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd) +static int cp15_tls_load_store(CPUARMState *env, DisasContext *s, uint32_t insn, uint32_t rd) { TCGv tmp; int cpn = (insn >> 16) & 0xf; @@ -2552,7 +2552,7 @@ static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, ui /* Disassemble system coprocessor (cp15) instruction. Return nonzero if instruction is not defined. */ -static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) +static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) { uint32_t rd; TCGv tmp, tmp2; @@ -2747,7 +2747,7 @@ static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size) /* Disassemble a VFP instruction. Returns nonzero if an error occurred (ie. an undefined instruction). */ -static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) +static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) { uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; int dp, veclen; @@ -3586,7 +3586,7 @@ static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y) } /* Return the mask of PSR bits set by a MSR instruction. */ -static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) { +static uint32_t msr_mask(CPUARMState *env, DisasContext *s, int flags, int spsr) { uint32_t mask; mask = 0; @@ -3946,7 +3946,7 @@ static struct { /* Translate a NEON load/store element instruction. Return nonzero if the instruction is invalid. */ -static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) +static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn) { int rd, rn, rm; int op; @@ -4622,7 +4622,7 @@ static const uint8_t neon_2rm_sizes[] = { We process data in a mixture of 32-bit and 64-bit chunks. Mostly we use 32-bit chunks so we can use normal scalar instructions. */ -static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) +static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t insn) { int op; int q; @@ -6387,7 +6387,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) return 0; } -static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) +static int disas_cp14_read(CPUARMState * env, DisasContext *s, uint32_t insn) { int crn = (insn >> 16) & 0xf; int crm = insn & 0xf; @@ -6445,7 +6445,7 @@ static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) return 1; } -static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn) +static int disas_cp14_write(CPUARMState * env, DisasContext *s, uint32_t insn) { int crn = (insn >> 16) & 0xf; int crm = insn & 0xf; @@ -6476,7 +6476,7 @@ static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn) return 1; } -static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn) +static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) { int cpnum; @@ -6696,7 +6696,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, } #endif -static void disas_arm_insn(CPUState * env, DisasContext *s) +static void disas_arm_insn(CPUARMState * env, DisasContext *s) { unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; TCGv tmp; @@ -7587,7 +7587,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); tmp3 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); + tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE)); gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); tcg_temp_free_i32(tmp3); tcg_temp_free_i32(tmp2); @@ -8077,7 +8077,7 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCG /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction is not legal. */ -static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) +static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1) { uint32_t insn, imm, shift, offset; uint32_t rd, rn, rm, rs; @@ -8488,7 +8488,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) case 0x10: /* sel */ tmp2 = load_reg(s, rm); tmp3 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); + tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE)); gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); tcg_temp_free_i32(tmp3); tcg_temp_free_i32(tmp2); @@ -9145,7 +9145,7 @@ illegal_op: return 1; } -static void disas_thumb_insn(CPUState *env, DisasContext *s) +static void disas_thumb_insn(CPUARMState *env, DisasContext *s) { uint32_t val, insn, op, rm, rn, rd, shift, cond; int32_t offset; @@ -9830,7 +9830,7 @@ undef: /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline void gen_intermediate_code_internal(CPUState *env, +static inline void gen_intermediate_code_internal(CPUARMState *env, TranslationBlock *tb, int search_pc) { @@ -9885,22 +9885,22 @@ static inline void gen_intermediate_code_internal(CPUState *env, /* A note on handling of the condexec (IT) bits: * * We want to avoid the overhead of having to write the updated condexec - * bits back to the CPUState for every instruction in an IT block. So: + * bits back to the CPUARMState for every instruction in an IT block. So: * (1) if the condexec bits are not already zero then we write - * zero back into the CPUState now. This avoids complications trying + * zero back into the CPUARMState now. This avoids complications trying * to do it at the end of the block. (For example if we don't do this * it's hard to identify whether we can safely skip writing condexec * at the end of the TB, which we definitely want to do for the case * where a TB doesn't do anything with the IT state at all.) * (2) if we are going to leave the TB then we call gen_set_condexec() - * which will write the correct value into CPUState if zero is wrong. + * which will write the correct value into CPUARMState if zero is wrong. * This is done both for leaving the TB at the end, and for leaving * it because of an exception we know will happen, which is done in * gen_exception_insn(). The latter is necessary because we need to * leave the TB with the PC/IT state just prior to execution of the * instruction which caused the exception. * (3) if we leave the TB unexpectedly (eg a data abort on a load) - * then the CPUState will be wrong and we need to reset it. + * then the CPUARMState will be wrong and we need to reset it. * This is handled in the same way as restoration of the * PC in these situations: we will be called again with search_pc=1 * and generate a mapping of the condexec bits for each PC in @@ -9909,7 +9909,7 @@ static inline void gen_intermediate_code_internal(CPUState *env, * * Note that there are no instructions which can read the condexec * bits, and none which can write non-static values to them, so - * we don't need to care about whether CPUState is correct in the + * we don't need to care about whether CPUARMState is correct in the * middle of a TB. */ @@ -10103,12 +10103,12 @@ done_generating: } } -void gen_intermediate_code(CPUState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 0); } -void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) +void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 1); } @@ -10118,7 +10118,7 @@ static const char *cpu_mode_names[16] = { "???", "???", "???", "und", "???", "???", "???", "sys" }; -void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, +void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf, int flags) { int i; @@ -10170,7 +10170,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, #endif } -void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) +void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos) { env->regs[15] = gen_opc_pc[pc_pos]; env->condexec_bits = gen_opc_condexec_bits[pc_pos]; |