Merge branch 'upstream-merge'

* upstream-merge: (88 commits)
  Add ability to force enable/disable of tools build
  Add ability to disable build of all targets
  RTC: Remove the current_tm field
  RTC: Get and set time without going through s->current_tm
  RTC: Do not fire timer periodically to catch next alarm
  RTC: Add divider reset support
  RTC: Update the RTC clock only when reading it
  vmstate: add VMSTATE_TIMER_V
  RTC: Update interrupt state when interrupts are masked/unmasked
  RTC: introduce RTC_CLOCK_RATE
  RTC: Rename rtc_timer_update
  RTC: Remove the logic to update time format when DM bit changed
  socket: don't attempt to reconnect a TCP socket in server mode
  use --libexecdir instead of ignoring it first and reinventing it later
  hw/mcf5206: Fix buffer overflow for MBAR read / write
  target-arm: Fix potential buffer overflow
  hw/wm8750: Fix potential buffer overflow
  kvm: i386: Add classic PCI device assignment
  kvm: i386: Add services required for PCI device assignment
  kvm: Introduce kvm_has_intx_set_mask
  ...

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>

1 files changed, 3 insertions, 13 deletions

diff --git a/target-mips/translate.c b/target-mips/translate.c
index b29341953..a884f751b 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12787,18 +12787,13 @@ void cpu_state_reset(CPUMIPSState *env)
     env->insn_flags = env->cpu_model->insn_flags;
 
 #if defined(CONFIG_USER_ONLY)
-    env->hflags = MIPS_HFLAG_UM;
+    env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
     /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
        hardware registers.  */
     env->CP0_HWREna |= 0x0000000F;
     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
-        env->hflags |= MIPS_HFLAG_FPU;
+        env->CP0_Status |= (1 << CP0St_CU1);
     }
-#ifdef TARGET_MIPS64
-    if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
-        env->hflags |= MIPS_HFLAG_F64;
-    }
-#endif
 #else
     if (env->hflags & MIPS_HFLAG_BMASK) {
         /* If the exception was raised from a delay slot,
@@ -12828,7 +12823,6 @@ void cpu_state_reset(CPUMIPSState *env)
     }
     /* Count register increments in debug mode, EJTAG version 1 */
     env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
-    env->hflags = MIPS_HFLAG_CP0;
 
     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
         int i;
@@ -12856,11 +12850,7 @@ void cpu_state_reset(CPUMIPSState *env)
         }
     }
 #endif
-#if defined(TARGET_MIPS64)
-    if (env->cpu_model->insn_flags & ISA_MIPS3) {
-        env->hflags |= MIPS_HFLAG_64;
-    }
-#endif
+    compute_hflags(env);
     env->exception_index = EXCP_NONE;
 }