From 9f7231bcee7ea3a5f64bf627e7b55cf7e33c7edb Mon Sep 17 00:00:00 2001 From: David Lin Date: Fri, 29 May 2015 17:31:29 +0800 Subject: Modify code to pass the checking of checkpatch.pl. Signed-off-by: David Lin --- Makefile | 2 +- Makefile.external | 2 +- mwl_debug.c | 88 ++++++----- mwl_debug.h | 23 +-- mwl_dev.h | 98 ++++++------ mwl_fwcmd.c | 465 ++++++++++++++++++++++++++++++++++-------------------- mwl_fwcmd.h | 10 +- mwl_fwdl.c | 63 +++++--- mwl_mac80211.c | 20 ++- mwl_main.c | 152 +++++++++++------- mwl_rx.c | 167 ++++++++++++-------- mwl_sysadpt.h | 6 +- mwl_tx.c | 347 +++++++++++++++++++++++----------------- 13 files changed, 865 insertions(+), 578 deletions(-) diff --git a/Makefile b/Makefile index cb06392..5771f78 100644 --- a/Makefile +++ b/Makefile @@ -17,7 +17,7 @@ EXTRA_CFLAGS+= -DMWL_DEBUG endif EXTRA_CFLAGS+= -I${KDIR} -EXTRA_CFLAGS+= -O2 -funroll-loops +EXTRA_CFLAGS+= -O2 -funroll-loops -DDEBUG EXTRA_CFLAGS+= -I${PWD} diff --git a/Makefile.external b/Makefile.external index cb06392..5771f78 100644 --- a/Makefile.external +++ b/Makefile.external @@ -17,7 +17,7 @@ EXTRA_CFLAGS+= -DMWL_DEBUG endif EXTRA_CFLAGS+= -I${KDIR} -EXTRA_CFLAGS+= -O2 -funroll-loops +EXTRA_CFLAGS+= -O2 -funroll-loops -DDEBUG EXTRA_CFLAGS+= -I${PWD} diff --git a/mwl_debug.c b/mwl_debug.c index 3402e99..22d5acf 100644 --- a/mwl_debug.c +++ b/mwl_debug.c @@ -38,10 +38,12 @@ DBG_CLASS_ENTER | \ DBG_CLASS_EXIT) +#define PRT_8BYTES "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" + /* PRIVATE VARIABLES */ -static u32 dbg_levels = 0; +static u32 dbg_levels; /* PUBLIC FUNCTION DEFINITION */ @@ -59,12 +61,15 @@ void mwl_debug_prt(u32 classlevel, const char *func, const char *format, ...) return; if ((level & dbg_levels) != level) { - if (class != DBG_CLASS_PANIC && class != DBG_CLASS_ERROR) + if (class != DBG_CLASS_PANIC && + class != DBG_CLASS_ERROR) return; } } - if ((debug_string = kmalloc(1024, GFP_ATOMIC)) == NULL) + debug_string = kmalloc(1024, GFP_ATOMIC); + + if (debug_string == NULL) return; if (format != NULL) { @@ -77,19 +82,19 @@ void mwl_debug_prt(u32 classlevel, const char *func, const char *format, ...) switch (class) { case DBG_CLASS_ENTER: - printk("Enter %s() ...\n", func); + pr_debug("Enter %s() ...\n", func); break; case DBG_CLASS_EXIT: - printk("... Exit %s()\n", func); + pr_debug("... Exit %s()\n", func); break; case DBG_CLASS_WARNING: - printk("WARNING: "); + pr_debug("WARNING: "); break; case DBG_CLASS_ERROR: - printk("ERROR: "); + pr_debug("ERROR: "); break; case DBG_CLASS_PANIC: - printk("PANIC: "); + pr_debug("PANIC: "); break; default: break; @@ -98,13 +103,14 @@ void mwl_debug_prt(u32 classlevel, const char *func, const char *format, ...) if (strlen(debug_string) > 0) { if (debug_string[strlen(debug_string)-1] == '\n') debug_string[strlen(debug_string)-1] = '\0'; - printk("%s(): %s\n", func, debug_string); + pr_debug("%s(): %s\n", func, debug_string); } kfree(debug_string); } -void mwl_debug_prtdata(u32 classlevel, const char *func, const void *data, int len, const char *format, ...) +void mwl_debug_prtdata(u32 classlevel, const char *func, + const void *data, int len, const char *format, ...) { unsigned char *dbg_string; unsigned char dbg_data[16] = ""; @@ -122,7 +128,9 @@ void mwl_debug_prtdata(u32 classlevel, const char *func, const void *data, int l if ((level & dbg_levels) != level) return; - if ((dbg_string = kmalloc(len + 1024, GFP_ATOMIC)) == NULL) + dbg_string = kmalloc(len + 1024, GFP_ATOMIC); + + if (dbg_string == NULL) return; if (format != NULL) { @@ -136,30 +144,32 @@ void mwl_debug_prtdata(u32 classlevel, const char *func, const void *data, int l if (strlen(dbg_string) > 0) { if (dbg_string[strlen(dbg_string) - 1] == '\n') dbg_string[strlen(dbg_string)-1] = '\0'; - printk("%s() %s\n", func, dbg_string); + pr_debug("%s() %s\n", func, dbg_string); } else { - printk("%s()\n", func); + pr_debug("%s()\n", func); } for (curr_byte = 0; curr_byte < len; curr_byte = curr_byte + 8) { if ((curr_byte + 8) < len) { - printk("0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", - *(memptr + curr_byte + 0), - *(memptr + curr_byte + 1), - *(memptr + curr_byte + 2), - *(memptr + curr_byte + 3), - *(memptr + curr_byte + 4), - *(memptr + curr_byte + 5), - *(memptr + curr_byte + 6), - *(memptr + curr_byte + 7)); + pr_debug(PRT_8BYTES, + *(memptr + curr_byte + 0), + *(memptr + curr_byte + 1), + *(memptr + curr_byte + 2), + *(memptr + curr_byte + 3), + *(memptr + curr_byte + 4), + *(memptr + curr_byte + 5), + *(memptr + curr_byte + 6), + *(memptr + curr_byte + 7)); } else { num_bytes = len - curr_byte; offset = curr_byte; - for (curr_byte = 0; curr_byte < num_bytes; curr_byte++) { - sprintf(dbg_data, "0x%02x ", *(memptr + offset + curr_byte)); + for (curr_byte = 0; curr_byte < num_bytes; + curr_byte++) { + sprintf(dbg_data, "0x%02x ", + *(memptr + offset + curr_byte)); strcat(dbg_string, dbg_data); } - printk("%s\n", dbg_string); + pr_debug("%s\n", dbg_string); break; } } @@ -174,25 +184,27 @@ void mwl_debug_dumpdata(const void *data, int len, char *marker) int num_bytes = 0; int offset = 0; - printk("%s\n", marker); + pr_debug("%s\n", marker); for (curr_byte = 0; curr_byte < len; curr_byte = curr_byte + 8) { if ((curr_byte + 8) < len) { - printk("0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", - *(memptr + curr_byte + 0), - *(memptr + curr_byte + 1), - *(memptr + curr_byte + 2), - *(memptr + curr_byte + 3), - *(memptr + curr_byte + 4), - *(memptr + curr_byte + 5), - *(memptr + curr_byte + 6), - *(memptr + curr_byte + 7)); + pr_debug(PRT_8BYTES, + *(memptr + curr_byte + 0), + *(memptr + curr_byte + 1), + *(memptr + curr_byte + 2), + *(memptr + curr_byte + 3), + *(memptr + curr_byte + 4), + *(memptr + curr_byte + 5), + *(memptr + curr_byte + 6), + *(memptr + curr_byte + 7)); } else { num_bytes = len - curr_byte; offset = curr_byte; - for (curr_byte = 0; curr_byte < num_bytes; curr_byte++) - printk("0x%02x ", *(memptr + offset + curr_byte)); - printk("\n\n"); + for (curr_byte = 0; curr_byte < num_bytes; + curr_byte++) + pr_debug("0x%02x ", + *(memptr + offset + curr_byte)); + pr_debug("\n\n"); break; } } diff --git a/mwl_debug.h b/mwl_debug.h index 423a409..53d04b4 100644 --- a/mwl_debug.h +++ b/mwl_debug.h @@ -63,36 +63,36 @@ #define DBG_CLASS_15 (1<<31) #define WLDBG_PRINT(...) \ - mwl_debug_prt(0, __FUNCTION__, __VA_ARGS__) + mwl_debug_prt(0, __func__, __VA_ARGS__) #ifdef MWL_DEBUG #define WLDBG_DUMP_DATA(classlevel, data, len) \ - mwl_debug_prtdata(classlevel|DBG_CLASS_DATA, __FUNCTION__, data, len, NULL) + mwl_debug_prtdata(classlevel|DBG_CLASS_DATA, __func__, data, len, NULL) #define WLDBG_ENTER(classlevel) \ - mwl_debug_prt(classlevel|DBG_CLASS_ENTER, __FUNCTION__, NULL) + mwl_debug_prt(classlevel|DBG_CLASS_ENTER, __func__, NULL) #define WLDBG_ENTER_INFO(classlevel, ...) \ - mwl_debug_prt(classlevel|DBG_CLASS_ENTER, __FUNCTION__, __VA_ARGS__) + mwl_debug_prt(classlevel|DBG_CLASS_ENTER, __func__, __VA_ARGS__) #define WLDBG_EXIT(classlevel) \ - mwl_debug_prt(classlevel|DBG_CLASS_EXIT, __FUNCTION__, NULL) + mwl_debug_prt(classlevel|DBG_CLASS_EXIT, __func__, NULL) #define WLDBG_EXIT_INFO(classlevel, ...) \ - mwl_debug_prt(classlevel|DBG_CLASS_EXIT, __FUNCTION__, __VA_ARGS__) + mwl_debug_prt(classlevel|DBG_CLASS_EXIT, __func__, __VA_ARGS__) #define WLDBG_INFO(classlevel, ...) \ - mwl_debug_prt(classlevel|DBG_CLASS_INFO, __FUNCTION__, __VA_ARGS__) + mwl_debug_prt(classlevel|DBG_CLASS_INFO, __func__, __VA_ARGS__) #define WLDBG_WARNING(classlevel, ...) \ - mwl_debug_prt(classlevel|DBG_CLASS_WARNING, __FUNCTION__, __VA_ARGS__) + mwl_debug_prt(classlevel|DBG_CLASS_WARNING, __func__, __VA_ARGS__) #define WLDBG_ERROR(classlevel, ...) \ - mwl_debug_prt(classlevel|DBG_CLASS_ERROR, __FUNCTION__, __VA_ARGS__) + mwl_debug_prt(classlevel|DBG_CLASS_ERROR, __func__, __VA_ARGS__) #define WLDBG_PANIC(classlevel, ...) \ - mwl_debug_prt(classlevel|DBG_CLASS_PANIC, __FUNCTION__, __VA_ARGS__) + mwl_debug_prt(classlevel|DBG_CLASS_PANIC, __func__, __VA_ARGS__) #else @@ -112,7 +112,8 @@ */ void mwl_debug_prt(u32 classlevel, const char *func, const char *format, ...); -void mwl_debug_prtdata(u32 classlevel, const char *func, const void *data, int len, const char *format, ...); +void mwl_debug_prtdata(u32 classlevel, const char *func, + const void *data, int len, const char *format, ...); void mwl_debug_dumpdata(const void *data, int len, char *marker); #endif /* _mwl_debug_h_ */ diff --git a/mwl_dev.h b/mwl_dev.h index 9157845..8895fa9 100644 --- a/mwl_dev.h +++ b/mwl_dev.h @@ -62,7 +62,7 @@ #define MACREG_A2HRIC_BIT_RX_PROBLEM 0x00000010 /* bit 4 */ #define MACREG_A2HRIC_BIT_RADIO_OFF 0x00000020 /* bit 5 */ #define MACREG_A2HRIC_BIT_RADIO_ON 0x00000040 /* bit 6 */ -#define MACREG_A2HRIC_BIT_RADAR_DETECT 0x00000080 /* bit 7 - IEEE80211_DH */ +#define MACREG_A2HRIC_BIT_RADAR_DETECT 0x00000080 /* bit 7 */ #define MACREG_A2HRIC_BIT_ICV_ERROR 0x00000100 /* bit 8 */ #define MACREG_A2HRIC_BIT_WEAKIV_ERROR 0x00000200 /* bit 9 */ #define MACREG_A2HRIC_BIT_QUEUE_EMPTY (1<<10) @@ -74,18 +74,18 @@ #define MACREG_A2HRIC_CONSEC_TXFAIL (1<<17) /* 15 taken by ISR_TXACK */ #define ISR_SRC_BITS ((MACREG_A2HRIC_BIT_RX_RDY) | \ - (MACREG_A2HRIC_BIT_TX_DONE) | \ - (MACREG_A2HRIC_BIT_OPC_DONE) | \ - (MACREG_A2HRIC_BIT_MAC_EVENT)| \ - (MACREG_A2HRIC_BIT_WEAKIV_ERROR)| \ - (MACREG_A2HRIC_BIT_ICV_ERROR)| \ - (MACREG_A2HRIC_BIT_SSU_DONE) | \ - (MACREG_A2HRIC_BIT_RADAR_DETECT)| \ - (MACREG_A2HRIC_BIT_CHAN_SWITCH)| \ - (MACREG_A2HRIC_BIT_TX_WATCHDOG)| \ - (MACREG_A2HRIC_BIT_QUEUE_EMPTY)| \ - (MACREG_A2HRIC_BA_WATCHDOG) | \ - (MACREG_A2HRIC_CONSEC_TXFAIL)) + (MACREG_A2HRIC_BIT_TX_DONE) | \ + (MACREG_A2HRIC_BIT_OPC_DONE) | \ + (MACREG_A2HRIC_BIT_MAC_EVENT)| \ + (MACREG_A2HRIC_BIT_WEAKIV_ERROR)| \ + (MACREG_A2HRIC_BIT_ICV_ERROR)| \ + (MACREG_A2HRIC_BIT_SSU_DONE) | \ + (MACREG_A2HRIC_BIT_RADAR_DETECT)| \ + (MACREG_A2HRIC_BIT_CHAN_SWITCH)| \ + (MACREG_A2HRIC_BIT_TX_WATCHDOG)| \ + (MACREG_A2HRIC_BIT_QUEUE_EMPTY)| \ + (MACREG_A2HRIC_BA_WATCHDOG) | \ + (MACREG_A2HRIC_CONSEC_TXFAIL)) #define MACREG_A2HRIC_BIT_MASK ISR_SRC_BITS @@ -125,7 +125,7 @@ #define EAGLE_TXD_XMITCTRL_USE_RATEINFO 0x1 #define EAGLE_TXD_XMITCTRL_DISABLE_AMPDU 0x2 #define EAGLE_TXD_XMITCTRL_ENABLE_AMPDU 0x4 -#define EAGLE_TXD_XMITCTRL_USE_MC_RATE 0x8 /* Use multicast data rate */ +#define EAGLE_TXD_XMITCTRL_USE_MC_RATE 0x8 #define NBR_BYTES_FW_RX_PREPEND_LEN 2 #define NBR_BYTES_FW_TX_PREPEND_LEN 2 @@ -161,12 +161,12 @@ /* vif and station */ -#define MAX_WEP_KEY_LEN 13 -#define NUM_WEP_KEYS 4 -#define MWL_MAX_TID 8 -#define MWL_VIF(_vif) ((struct mwl_vif *)&((_vif)->drv_priv)) -#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8)) -#define MWL_STA(_sta) ((struct mwl_sta *)&((_sta)->drv_priv)) +#define MAX_WEP_KEY_LEN 13 +#define NUM_WEP_KEYS 4 +#define MWL_MAX_TID 8 +#define MWL_VIF(_vif) ((struct mwl_vif *)&((_vif)->drv_priv)) +#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8)) +#define MWL_STA(_sta) ((struct mwl_sta *)&((_sta)->drv_priv)) /* TYPE DEFINITION */ @@ -220,18 +220,18 @@ struct mwl_hw_data { }; struct mwl_rate_info { - u32 format:2; /* 0 = Legacy, 1 = 11n, 2 = 11ac */ + u32 format:2; /* 0 = Legacy, 1 = 11n, 2 = 11ac */ u32 stbc:1; u32 rsvd1:1; - u32 bandwidth:2; /* 0 = 20 MHz, 1 = 40 MHz, 2 = 80 MHz */ - u32 short_gi:1; /* 0 = standard guard interval, 1 = short */ + u32 bandwidth:2; /* 0 = 20 MHz, 1 = 40 MHz, 2 = 80 MHz */ + u32 short_gi:1; /* 0 = standard guard interval, 1 = short */ u32 rsvd2:1; u32 rate_id_mcs:7; - u32 preamble_type:1; /* Preambletype 0 = Long, 1 = Short; */ + u32 preamble_type:1; /* Preambletype 0 = Long, 1 = Short; */ u32 power_id:6; - u32 adv_coding:1; /* ldpc */ + u32 adv_coding:1; /* ldpc */ u32 bf:1; - u32 ant_select:8; /* Bitmap to select one of the transmit antenna */ + u32 ant_select:8; /* Bitmap to select one of the transmit antenna */ } __packed; struct mwl_tx_desc { @@ -245,7 +245,7 @@ struct mwl_tx_desc { u32 sap_pkt_info; struct mwl_rate_info rate_info; u8 type; - u8 xmit_control; /* bit 0: use rateinfo, bit 1: disable ampdu */ + u8 xmit_control; /* bit 0: use rateinfo, bit 1: disable ampdu */ u16 reserved; u32 tcpack_sn; u32 tcpack_src_dst; @@ -275,12 +275,12 @@ struct mwl_hw_noise_floor_info { } __packed; struct mwl_rxrate_info { - u16 format:3; /* 0: 11a, 1: 11b, 2: 11n, 4: 11ac */ - u16 nss:2; /* number space spectrum */ - u16 bw:2; /* 0: ht20, 1: ht40, 2: ht80 */ - u16 gi:1; /* 0: long interval, 1: short interval*/ - u16 rt:8; /* 11a/11b: 1,2,5,11,22,6,9,12,18,24,36,48,54,72*/ -} __packed; /* 11n/11ac: MCS */ + u16 format:3; /* 0: 11a, 1: 11b, 2: 11n, 4: 11ac */ + u16 nss:2; /* number space spectrum */ + u16 bw:2; /* 0: ht20, 1: ht40, 2: ht80 */ + u16 gi:1; /* 0: long interval, 1: short interval*/ + u16 rt:8; /* 11a/11b: 1,2,5,11,22,6,9,12,18,24,36,48,54,72*/ +} __packed; /* 11n/11ac: MCS */ struct mwl_rx_desc { u16 pkt_len; /* total length of received data */ @@ -297,7 +297,9 @@ struct mwl_rx_desc { u8 status; /* status field containing USED bit */ u8 channel; /* channel this pkt was received on */ u8 rx_control; /* the control element of the desc */ - /* above are 32bits aligned and is same as FW, RxControl put at end for sync */ + /* above are 32bits aligned and is same as FW, RxControl put at end + * for sync + */ struct sk_buff *psk_buff; /* associated sk_buff for Linux */ void *pbuff_data; /* virtual address of payload data */ struct mwl_rx_desc *pnext; /* virtual address of next RX desc */ @@ -345,7 +347,7 @@ struct mwl_priv { u16 txantenna2; u8 powinited; u16 max_tx_pow[SYSADPT_TX_POWER_LEVEL_TOTAL]; /* max tx power (dBm) */ - u16 target_powers[SYSADPT_TX_POWER_LEVEL_TOTAL]; /* target powers (dBm) */ + u16 target_powers[SYSADPT_TX_POWER_LEVEL_TOTAL]; /* target powers */ u8 cal_tbl[200]; struct pci_dev *pdev; void *iobase0; /* MEM Base Address Register 0 */ @@ -355,12 +357,14 @@ struct mwl_priv { dma_addr_t pphys_cmd_buf; /* pointer to CmdBuf (physical) */ bool in_send_cmd; int irq; - struct mwl_hw_data hw_data; /* Adapter HW specific info */ - struct mwl_desc_data desc_data[SYSADPT_NUM_OF_DESC_DATA]; /* various descriptor data */ + struct mwl_hw_data hw_data; /* Adapter HW specific info */ + /* various descriptor data */ + struct mwl_desc_data desc_data[SYSADPT_NUM_OF_DESC_DATA]; struct sk_buff_head txq[SYSADPT_NUM_OF_DESC_DATA]; - struct sk_buff_head delay_freeq; - int fw_desc_cnt[SYSADPT_NUM_OF_DESC_DATA]; /* number of descriptors owned by fw at any one time */ - struct mwl_locks locks; /* various spinlocks */ + struct sk_buff_head delay_q; + /* number of descriptors owned by fw at any one time */ + int fw_desc_cnt[SYSADPT_NUM_OF_DESC_DATA]; + struct mwl_locks locks; /* various spinlocks */ struct tasklet_struct tx_task; struct tasklet_struct rx_task; int txq_limit; @@ -392,7 +396,7 @@ struct mwl_priv { struct beacon_info { bool valid; u16 cap_info; - u8 bss_basic_rate_set[SYSADPT_MAX_DATA_RATES_G]; + u8 b_rate_set[SYSADPT_MAX_DATA_RATES_G]; u8 op_rate_set[SYSADPT_MAX_DATA_RATES_G]; u8 ie_wmm_len; /* Keep WMM IE */ u8 *ie_wmm_ptr; @@ -411,16 +415,18 @@ struct beacon_info { struct mwl_vif { struct list_head list; struct ieee80211_vif *vif; - int macid; /* Firmware macid for this vif. */ - u16 seqno; /* Non AMPDU sequence number assigned by driver. */ - struct { /* Saved WEP keys */ + int macid; /* Firmware macid for this vif. */ + u16 seqno; /* Non AMPDU sequence number assigned by driver. */ + struct { /* Saved WEP keys */ u8 enabled; u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN]; } wep_key_conf[NUM_WEP_KEYS]; u8 bssid[ETH_ALEN]; /* BSSID */ u8 sta_mac[ETH_ALEN]; /* Station mac address */ - bool is_hw_crypto_enabled; /* A flag to indicate is HW crypto is enabled for this bssid */ - bool is_sta; /* Indicate if this is station mode */ + /* A flag to indicate is HW crypto is enabled for this bssid */ + bool is_hw_crypto_enabled; + /* Indicate if this is station mode */ + bool is_sta; struct beacon_info beacon_info; u16 iv16; u32 iv32; diff --git a/mwl_fwcmd.c b/mwl_fwcmd.c index 58edac1..9847f20 100644 --- a/mwl_fwcmd.c +++ b/mwl_fwcmd.c @@ -20,6 +20,8 @@ * */ +#include + #include "mwl_sysadpt.h" #include "mwl_dev.h" #include "mwl_debug.h" @@ -66,11 +68,16 @@ * Define general result code for each command */ #define HOSTCMD_RESULT_OK 0x0000 /* OK */ -#define HOSTCMD_RESULT_ERROR 0x0001 /* Genenral error */ -#define HOSTCMD_RESULT_NOT_SUPPORT 0x0002 /* Command is not valid */ -#define HOSTCMD_RESULT_PENDING 0x0003 /* Command is pending (will be processed) */ -#define HOSTCMD_RESULT_BUSY 0x0004 /* System is busy (command ignored) */ -#define HOSTCMD_RESULT_PARTIAL_DATA 0x0005 /* Data buffer is not big enough */ +/* Genenral error */ +#define HOSTCMD_RESULT_ERROR 0x0001 +/* Command is not valid */ +#define HOSTCMD_RESULT_NOT_SUPPORT 0x0002 +/* Command is pending (will be processed) */ +#define HOSTCMD_RESULT_PENDING 0x0003 +/* System is busy (command ignored) */ +#define HOSTCMD_RESULT_BUSY 0x0004 +/* Data buffer is not big enough */ +#define HOSTCMD_RESULT_PARTIAL_DATA 0x0005 /* * Define channel related constants @@ -89,14 +96,22 @@ #define EXT_CH_BELOW_CTRL_CH 0x3 #define NO_EXT_CHANNEL 0x0 -#define ACT_PRIMARY_CHAN_0 0 /* active primary 1st 20MHz channel */ -#define ACT_PRIMARY_CHAN_1 1 /* active primary 2nd 20MHz channel */ -#define ACT_PRIMARY_CHAN_2 2 /* active primary 3rd 20MHz channel */ -#define ACT_PRIMARY_CHAN_3 3 /* active primary 4th 20MHz channel */ -#define ACT_PRIMARY_CHAN_4 4 /* active primary 5th 20MHz channel */ -#define ACT_PRIMARY_CHAN_5 5 /* active primary 6th 20MHz channel */ -#define ACT_PRIMARY_CHAN_6 6 /* active primary 7th 20MHz channel */ -#define ACT_PRIMARY_CHAN_7 7 /* active primary 8th 20MHz channel */ +/* active primary 1st 20MHz channel */ +#define ACT_PRIMARY_CHAN_0 0 +/* active primary 2nd 20MHz channel */ +#define ACT_PRIMARY_CHAN_1 1 +/* active primary 3rd 20MHz channel */ +#define ACT_PRIMARY_CHAN_2 2 +/* active primary 4th 20MHz channel */ +#define ACT_PRIMARY_CHAN_3 3 +/* active primary 5th 20MHz channel */ +#define ACT_PRIMARY_CHAN_4 4 +/* active primary 6th 20MHz channel */ +#define ACT_PRIMARY_CHAN_5 5 +/* active primary 7th 20MHz channel */ +#define ACT_PRIMARY_CHAN_6 6 +/* active primary 8th 20MHz channel */ +#define ACT_PRIMARY_CHAN_7 7 /* * Define rate related constants @@ -115,15 +130,23 @@ #define MAX_ENCR_KEY_LENGTH 16 #define MIC_KEY_LENGTH 8 -#define KEY_TYPE_ID_WEP 0x00 /* Key type is WEP */ -#define KEY_TYPE_ID_TKIP 0x01 /* Key type is TKIP */ -#define KEY_TYPE_ID_AES 0x02 /* Key type is AES-CCMP */ - -#define ENCR_KEY_FLAG_TXGROUPKEY 0x00000004 /* Group key for TX */ -#define ENCR_KEY_FLAG_PAIRWISE 0x00000008 /* pairwise */ -#define ENCR_KEY_FLAG_TSC_VALID 0x00000040 /* Sequence counters are valid */ -#define ENCR_KEY_FLAG_WEP_TXKEY 0x01000000 /* Tx key for WEP */ -#define ENCR_KEY_FLAG_MICKEY_VALID 0x02000000 /* Tx/Rx MIC keys are valid */ +/* Key type is WEP */ +#define KEY_TYPE_ID_WEP 0x00 +/* Key type is TKIP */ +#define KEY_TYPE_ID_TKIP 0x01 +/* Key type is AES-CCMP */ +#define KEY_TYPE_ID_AES 0x02 + +/* Group key for TX */ +#define ENCR_KEY_FLAG_TXGROUPKEY 0x00000004 +/* pairwise */ +#define ENCR_KEY_FLAG_PAIRWISE 0x00000008 +/* Sequence counters are valid */ +#define ENCR_KEY_FLAG_TSC_VALID 0x00000040 +/* Tx key for WEP */ +#define ENCR_KEY_FLAG_WEP_TXKEY 0x01000000 +/* Tx/Rx MIC keys are valid */ +#define ENCR_KEY_FLAG_MICKEY_VALID 0x02000000 /* * Define block ack related constants @@ -140,8 +163,8 @@ /* Misc */ -#define MWL_SPIN_LOCK(X) SPIN_LOCK_IRQSAVE(X, flags) -#define MWL_SPIN_UNLOCK(X) SPIN_UNLOCK_IRQRESTORE(X, flags) +#define MWL_SPIN_LOCK(X) SPIN_LOCK_IRQSAVE(X, flags) +#define MWL_SPIN_UNLOCK(X) SPIN_UNLOCK_IRQRESTORE(X, flags) #define MAX_ENCR_KEY_LENGTH 16 #define MIC_KEY_LENGTH 8 @@ -231,20 +254,40 @@ struct hostcmd_cmd_get_hw_spec { struct hostcmd_cmd_set_hw_spec { struct hostcmd_header cmd_hdr; - u8 version; /* HW revision */ - u8 host_if; /* Host interface */ - u16 num_mcast_addr; /* Max. number of Multicast address FW can handle */ - u8 permanent_addr[ETH_ALEN]; /* MAC address */ - u16 region_code; /* Region Code */ - u32 fw_release_num; /* 4 byte of FW release number, example 0x1234=1.2.3.4 */ - u32 fw_awake_cookie; /* Firmware awake cookie - used to ensure that the device is not in sleep mode */ - u32 device_caps; /* Device capabilities (see above) */ - u32 rxpd_wr_ptr; /* Rx shared memory queue */ - u32 num_tx_queues; /* Actual number of TX queues in WcbBase array */ - u32 wcb_base[SYSADPT_NUM_OF_DESC_DATA]; /* TX WCB Rings */ - u32 max_amsdu_size:2; /* Max AMSDU size (00 - AMSDU Disabled, 01 - 4K, 10 - 8K, 11 - not defined) */ - u32 implicit_ampdu_ba:1; /* Indicates supported AMPDU type (1 = implicit, 0 = explicit (default)) */ - u32 disablembss:1; /* indicates mbss features disable in FW */ + /* HW revision */ + u8 version; + /* Host interface */ + u8 host_if; + /* Max. number of Multicast address FW can handle */ + u16 num_mcast_addr; + /* MAC address */ + u8 permanent_addr[ETH_ALEN]; + /* Region Code */ + u16 region_code; + /* 4 byte of FW release number, example 0x1234=1.2.3.4 */ + u32 fw_release_num; + /* Firmware awake cookie - used to ensure that the device + * is not in sleep mode + */ + u32 fw_awake_cookie; + /* Device capabilities (see above) */ + u32 device_caps; + /* Rx shared memory queue */ + u32 rxpd_wr_ptr; + /* Actual number of TX queues in WcbBase array */ + u32 num_tx_queues; + /* TX WCB Rings */ + u32 wcb_base[SYSADPT_NUM_OF_DESC_DATA]; + /* Max AMSDU size (00 - AMSDU Disabled, + * 01 - 4K, 10 - 8K, 11 - not defined) + */ + u32 max_amsdu_size:2; + /* Indicates supported AMPDU type + * (1 = implicit, 0 = explicit (default)) + */ + u32 implicit_ampdu_ba:1; + /* indicates mbss features disable in FW */ + u32 disablembss:1; u32 host_form_beacon:1; u32 host_form_probe_response:1; u32 host_power_save:1; @@ -280,7 +323,8 @@ struct hostcmd_cmd_802_11_get_stat { u32 tx_done; u32 tx_done_buf_try_put; u32 tx_done_buf_put; - u32 wait_for_tx_buf; /* Put size of requested buffer in here */ + /* Put size of requested buffer in here */ + u32 wait_for_tx_buf; u32 tx_attempts; u32 tx_successes; u32 tx_fragments; @@ -305,7 +349,8 @@ struct hostcmd_cmd_802_11_get_stat { struct hostcmd_cmd_802_11_radio_control { struct hostcmd_header cmd_hdr; u16 action; - u16 control; /* @bit0: 1/0,on/off, @bit1: 1/0, long/short @bit2: 1/0,auto/fix */ + /* @bit0: 1/0,on/off, @bit1: 1/0, long/short @bit2: 1/0,auto/fix */ + u16 control; u16 radio_on; } __packed; @@ -330,7 +375,7 @@ struct hostcmd_cmd_802_11_tx_power { struct hostcmd_cmd_802_11_rf_antenna { struct hostcmd_header cmd_hdr; u16 action; - u16 antenna_mode; /* Number of antennas or 0xffff(diversity) */ + u16 antenna_mode; /* Number of antennas or 0xffff(diversity) */ } __packed; /* @@ -347,9 +392,14 @@ struct hostcmd_cmd_broadcast_ssid_enable { */ struct chnl_flags_11ac { - u32 freq_band:6; /* bit0=1: 2.4GHz,bit1=1: 4.9GHz,bit2=1: 5GHz,bit3=1: 5.2GHz, */ - u32 chnl_width:5; /* bit6=1:10MHz, bit7=1:20MHz, bit8=1:40MHz */ - u32 act_primary:3; /* 000: 1st 20MHz chan, 001:2nd 20MHz chan, 011:3rd 20MHz chan, 100:4th 20MHz chan */ + /* bit0=1: 2.4GHz,bit1=1: 4.9GHz,bit2=1: 5GHz,bit3=1: 5.2GHz, */ + u32 freq_band:6; + /* bit6=1:10MHz, bit7=1:20MHz, bit8=1:40MHz */ + u32 chnl_width:5; + /* 000: 1st 20MHz chan, 001:2nd 20MHz chan, 011:3rd 20MHz chan, + * 100:4th 20MHz chan + */ + u32 act_primary:3; u32 reserved:18; } __packed; @@ -396,7 +446,8 @@ struct hostcmd_cmd_802_11_rts_thsd { struct hostcmd_cmd_set_edca_params { struct hostcmd_header cmd_hdr; - u16 action; /* 0 = get all, 0x1 =set CWMin/Max, 0x2 = set TXOP , 0x4 =set AIFSN */ + /* 0 = get all, 0x1 =set CWMin/Max, 0x2 = set TXOP , 0x4 =set AIFSN */ + u16 action; u16 txop; /* in unit of 32 us */ u32 cw_max; /* 0~15 */ u32 cw_min; /* 0~15 */ @@ -418,20 +469,27 @@ struct hostcmd_cmd_set_wmm_mode { */ struct fix_rate_flag { /* lower rate after the retry count */ - u32 fix_rate_type; /* 0: legacy, 1: HT */ - u32 retry_count_valid; /* 0: retry count is not valid, 1: use retry count specified */ + /* 0: legacy, 1: HT */ + u32 fix_rate_type; + /* 0: retry count is not valid, 1: use retry count specified */ + u32 retry_count_valid; } __packed; struct fix_rate_entry { struct fix_rate_flag fix_rate_type_flags; - u32 fixed_rate; /* depending on the flags above, this can be either a legacy rate(not index) or an MCS code. */ + /* depending on the flags above, this can be either a legacy + * rate(not index) or an MCS code. + */ + u32 fixed_rate; u32 retry_count; } __packed; struct hostcmd_cmd_set_fixed_rate { struct hostcmd_header cmd_hdr; - u32 action; /* HOSTCMD_ACT_NOT_USE_FIXED_RATE 0x0002 */ - u32 allow_rate_drop; /* use fixed rate specified but firmware can drop to */ + /* HOSTCMD_ACT_NOT_USE_FIXED_RATE 0x0002 */ + u32 action; + /* use fixed rate specified but firmware can drop to */ + u32 allow_rate_drop; u32 entry_count; struct fix_rate_entry fixed_rate_table[4]; u8 multicast_rate; @@ -619,7 +677,7 @@ struct start_cmd { union phy_params phy_param_set; u16 probe_delay; u16 cap_info; - u8 bss_basic_rate_set[SYSADPT_MAX_DATA_RATES_G]; + u8 b_rate_set[SYSADPT_MAX_DATA_RATES_G]; u8 op_rate_set[SYSADPT_MAX_DATA_RATES_G]; struct rsn_ie rsn_ie; struct rsn48_ie rsn48_ie; @@ -700,7 +758,8 @@ struct peer_info { u32 tx_bf_capabilities; /* EXBF_SUPPORT */ u32 vht_max_rx_mcs; u32 vht_cap; - u8 vht_rx_channel_width; /* 0:20Mhz, 1:40Mhz, 2:80Mhz, 3:160 or 80+80Mhz */ + /* 0:20Mhz, 1:40Mhz, 2:80Mhz, 3:160 or 80+80Mhz */ + u8 vht_rx_channel_width; } __packed; struct hostcmd_cmd_set_new_stn { @@ -751,7 +810,9 @@ struct encr_tkip_seqcnt { } __packed; struct tkip_type_key { - /* TKIP Key material. Key type (group or pairwise key) is determined by flags */ + /* TKIP Key material. Key type (group or pairwise key) is + * determined by flags + */ /* in KEY_PARAM_SET structure. */ u8 key_material[MAX_ENCR_KEY_LENGTH]; /* MIC keys */ @@ -819,7 +880,9 @@ struct create_ba_params { struct ba_stream_flags flags; /* idle threshold */ u32 idle_thrs; - /* block ack transmit threshold (after how many pkts should we send BAR?) */ + /* block ack transmit threshold (after how many pkts should we + * send BAR?) + */ u32 bar_thrs; /* receiver window size */ u32 window_size; @@ -833,11 +896,14 @@ struct create_ba_params { u8 queue_id; u8 param_info; /* returned by firmware - firmware context pointer. */ - /* this context pointer will be passed to firmware for all future commands. */ + /* this context pointer will be passed to firmware for all + * future commands. + */ struct ba_context fw_ba_context; u8 reset_seq_no; /** 0 or 1**/ u16 current_seq; - u8 sta_src_mac_addr[ETH_ALEN]; /* This is for virtual station in Sta proxy mode for V6FW */ + /* This is for virtual station in Sta proxy mode for V6FW */ + u8 sta_src_mac_addr[ETH_ALEN]; } __packed; /* new transmit sequence number information */ @@ -889,7 +955,8 @@ struct hostcmd_cmd_dwds_enable { struct hostcmd_cmd_fw_flush_timer { struct hostcmd_header cmd_hdr; - u32 value; /* 0 -- Disable. > 0 -- holds time value in usecs. */ + /* 0 -- Disable. > 0 -- holds time value in usecs. */ + u32 value; } __packed; /* @@ -909,19 +976,23 @@ static int mwl_fwcmd_exec_cmd(struct mwl_priv *priv, unsigned short cmd); static void mwl_fwcmd_send_cmd(struct mwl_priv *priv); static int mwl_fwcmd_wait_complete(struct mwl_priv *priv, unsigned short cmd); -static int mwl_fwcmd_802_11_radio_control(struct mwl_priv *priv, bool enable, bool force); +static int mwl_fwcmd_802_11_radio_control(struct mwl_priv *priv, + bool enable, bool force); static int mwl_fwcmd_get_tx_powers(struct mwl_priv *priv, u16 *powlist, u16 ch, u16 band, u16 width, u16 sub_ch); -static int mwl_fwcmd_set_tx_powers(struct mwl_priv *priv, u16 txpow[], u8 action, - u16 ch, u16 band, u16 width, u16 sub_ch); +static int mwl_fwcmd_set_tx_powers(struct mwl_priv *priv, u16 txpow[], + u8 action, u16 ch, u16 band, + u16 width, u16 sub_ch); static u8 mwl_fwcmd_get_80m_pri_chnl_offset(u8 channel); static void mwl_fwcmd_parse_beacon(struct mwl_priv *priv, struct mwl_vif *vif, u8 *beacon, int len); static int mwl_fwcmd_set_ies(struct mwl_priv *priv, struct mwl_vif *mwl_vif); -static int mwl_fwcmd_set_ap_beacon(struct mwl_priv *priv, struct mwl_vif *mwl_vif, +static int mwl_fwcmd_set_ap_beacon(struct mwl_priv *priv, + struct mwl_vif *mwl_vif, struct ieee80211_bss_conf *bss_conf); static int mwl_fwcmd_encryption_set_cmd_info(struct hostcmd_cmd_set_key *cmd, - u8 *addr, struct ieee80211_key_conf *key); + u8 *addr, + struct ieee80211_key_conf *key); #ifdef MWL_DEBUG static char *mwl_fwcmd_get_cmd_string(unsigned short cmd); @@ -941,7 +1012,8 @@ void mwl_fwcmd_reset(struct ieee80211_hw *hw) BUG_ON(!priv); if (mwl_fwcmd_chk_adapter(priv)) { - writel(ISR_RESET, priv->iobase1 + MACREG_REG_H2A_INTERRUPT_EVENTS); + writel(ISR_RESET, + priv->iobase1 + MACREG_REG_H2A_INTERRUPT_EVENTS); } WLDBG_EXIT(DBG_LEVEL_2); @@ -958,7 +1030,8 @@ void mwl_fwcmd_int_enable(struct ieee80211_hw *hw) BUG_ON(!priv); if (mwl_fwcmd_chk_adapter(priv)) { - writel(0x00, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_MASK); + writel(0x00, + priv->iobase1 + MACREG_REG_A2H_INTERRUPT_MASK); writel((MACREG_A2HRIC_BIT_MASK), priv->iobase1 + MACREG_REG_A2H_INTERRUPT_MASK); } @@ -977,7 +1050,8 @@ void mwl_fwcmd_int_disable(struct ieee80211_hw *hw) BUG_ON(!priv); if (mwl_fwcmd_chk_adapter(priv)) { - writel(0x00, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_MASK); + writel(0x00, + priv->iobase1 + MACREG_REG_A2H_INTERRUPT_MASK); } WLDBG_EXIT(DBG_LEVEL_2); @@ -1015,14 +1089,18 @@ int mwl_fwcmd_get_hw_specs(struct ieee80211_hw *hw) WLDBG_PRINT("repeat command = %x", (unsigned int)pcmd); } - memcpy(&priv->hw_data.mac_addr[0], pcmd->permanent_addr, ETH_ALEN); - priv->desc_data[0].wcb_base = ENDIAN_SWAP32(pcmd->wcb_base0) & 0x0000ffff; + ether_addr_copy(&priv->hw_data.mac_addr[0], pcmd->permanent_addr); + priv->desc_data[0].wcb_base = + ENDIAN_SWAP32(pcmd->wcb_base0) & 0x0000ffff; #if SYSADPT_NUM_OF_DESC_DATA > 3 for (i = 1; i < SYSADPT_TOTAL_TX_QUEUES; i++) - priv->desc_data[i].wcb_base = ENDIAN_SWAP32(pcmd->wcb_base[i - 1]) & 0x0000ffff; + priv->desc_data[i].wcb_base = + ENDIAN_SWAP32(pcmd->wcb_base[i - 1]) & 0x0000ffff; #endif - priv->desc_data[0].rx_desc_read = ENDIAN_SWAP32(pcmd->rxpd_rd_ptr) & 0x0000ffff; - priv->desc_data[0].rx_desc_write = ENDIAN_SWAP32(pcmd->rxpd_wr_ptr) & 0x0000ffff; + priv->desc_data[0].rx_desc_read = + ENDIAN_SWAP32(pcmd->rxpd_rd_ptr) & 0x0000ffff; + priv->desc_data[0].rx_desc_write = + ENDIAN_SWAP32(pcmd->rxpd_wr_ptr) & 0x0000ffff; priv->hw_data.region_code = ENDIAN_SWAP16(pcmd->region_code) & 0x00ff; priv->hw_data.fw_release_num = ENDIAN_SWAP32(pcmd->fw_release_num); priv->hw_data.max_num_tx_desc = ENDIAN_SWAP16(pcmd->num_wcb); @@ -1056,14 +1134,21 @@ int mwl_fwcmd_set_hw_specs(struct ieee80211_hw *hw) /* Info for debugging */ - WLDBG_PRINT("%s ...", __FUNCTION__); - WLDBG_PRINT(" -->pPhysTxRing[0] = %x", priv->desc_data[0].pphys_tx_ring); - WLDBG_PRINT(" -->pPhysTxRing[1] = %x", priv->desc_data[1].pphys_tx_ring); - WLDBG_PRINT(" -->pPhysTxRing[2] = %x", priv->desc_data[2].pphys_tx_ring); - WLDBG_PRINT(" -->pPhysTxRing[3] = %x", priv->desc_data[3].pphys_tx_ring); - WLDBG_PRINT(" -->pPhysRxRing = %x", priv->desc_data[0].pphys_rx_ring); - WLDBG_PRINT(" -->numtxq %d wcbperq %d totalrxwcb %d", - SYSADPT_NUM_OF_DESC_DATA, SYSADPT_MAX_NUM_TX_DESC, SYSADPT_MAX_NUM_RX_DESC); + WLDBG_PRINT("%s ...", __func__); + WLDBG_PRINT(" -->pPhysTxRing[0] = %x", + priv->desc_data[0].pphys_tx_ring); + WLDBG_PRINT(" -->pPhysTxRing[1] = %x", + priv->desc_data[1].pphys_tx_ring); + WLDBG_PRINT(" -->pPhysTxRing[2] = %x", + priv->desc_data[2].pphys_tx_ring); + WLDBG_PRINT(" -->pPhysTxRing[3] = %x", + priv->desc_data[3].pphys_tx_ring); + WLDBG_PRINT(" -->pPhysRxRing = %x", + priv->desc_data[0].pphys_rx_ring); + WLDBG_PRINT(" -->numtxq %d wcbperq %d totalrxwcb %d", + SYSADPT_NUM_OF_DESC_DATA, + SYSADPT_MAX_NUM_TX_DESC, + SYSADPT_MAX_NUM_RX_DESC); pcmd = (struct hostcmd_cmd_set_hw_spec *)&priv->pcmd_buf[0]; @@ -1075,7 +1160,8 @@ int mwl_fwcmd_set_hw_specs(struct ieee80211_hw *hw) pcmd->wcb_base[0] = ENDIAN_SWAP32(priv->desc_data[0].pphys_tx_ring); #if SYSADPT_NUM_OF_DESC_DATA > 3 for (i = 1; i < SYSADPT_TOTAL_TX_QUEUES; i++) - pcmd->wcb_base[i] = ENDIAN_SWAP32(priv->desc_data[i].pphys_tx_ring); + pcmd->wcb_base[i] = + ENDIAN_SWAP32(priv->desc_data[i].pphys_tx_ring); #endif pcmd->tx_wcb_num_per_queue = ENDIAN_SWAP32(SYSADPT_MAX_NUM_TX_DESC); pcmd->num_tx_queues = ENDIAN_SWAP32(SYSADPT_NUM_OF_DESC_DATA); @@ -1223,7 +1309,8 @@ int mwl_fwcmd_max_tx_power(struct ieee80211_hw *hw, reduce_val = 6; /* 25% -6db */ break; default: - reduce_val = 0xff; /* larger than case 3, pCmd->MaxPowerLevel is min */ + /* larger than case 3, pCmd->MaxPowerLevel is min */ + reduce_val = 0xff; break; } @@ -1311,7 +1398,8 @@ int mwl_fwcmd_tx_power(struct ieee80211_hw *hw, reduce_val = 6; /* 25% -6db */ break; default: - reduce_val = 0xff; /* larger than case 3, pCmd->MaxPowerLevel is min */ + /* larger than case 3, pCmd->MaxPowerLevel is min */ + reduce_val = 0xff; break; } @@ -1341,25 +1429,31 @@ int mwl_fwcmd_tx_power(struct ieee80211_hw *hw, /* search tx power table if exist */ for (index = 0; index < SYSADPT_MAX_NUM_CHANNELS; index++) { + struct mwl_tx_pwr_tbl *tx_pwr; + + tx_pwr = &priv->tx_pwr_tbl[index]; + /* do nothing if table is not loaded */ - if (priv->tx_pwr_tbl[index].channel == 0) + if (tx_pwr->channel == 0) break; - if (priv->tx_pwr_tbl[index].channel == channel->hw_value) { - priv->cdd = priv->tx_pwr_tbl[index].cdd; - priv->txantenna2 = priv->tx_pwr_tbl[index].txantenna2; + if (tx_pwr->channel == channel->hw_value) { + priv->cdd = tx_pwr->cdd; + priv->txantenna2 = tx_pwr->txantenna2; - if (priv->tx_pwr_tbl[index].setcap) + if (tx_pwr->setcap) priv->powinited = 0x01; else priv->powinited = 0x02; for (i = 0; i < SYSADPT_TX_POWER_LEVEL_TOTAL; i++) { - if (priv->tx_pwr_tbl[index].setcap) - priv->max_tx_pow[i] = priv->tx_pwr_tbl[index].tx_power[i]; + if (tx_pwr->setcap) + priv->max_tx_pow[i] = + tx_pwr->tx_power[i]; else - priv->target_powers[i] = priv->tx_pwr_tbl[index].tx_power[i]; + priv->target_powers[i] = + tx_pwr->tx_power[i]; } found = 1; @@ -1383,8 +1477,9 @@ int mwl_fwcmd_tx_power(struct ieee80211_hw *hw, for (i = 0; i < SYSADPT_TX_POWER_LEVEL_TOTAL; i++) { if (found) { - if ((priv->tx_pwr_tbl[index].setcap) - && (priv->tx_pwr_tbl[index].tx_power[i] > priv->max_tx_pow[i])) + if ((priv->tx_pwr_tbl[index].setcap) && + (priv->tx_pwr_tbl[index].tx_power[i] > + priv->max_tx_pow[i])) tmp = priv->max_tx_pow[i]; else tmp = priv->tx_pwr_tbl[index].tx_power[i]; @@ -1430,7 +1525,7 @@ int mwl_fwcmd_rf_antenna(struct ieee80211_hw *hw, int dir, int antenna) if (dir == WL_ANTENNATYPE_RX) { u8 rx_antenna = 4; /* if auto, set 4 rx antennas in SC2 */ - + if (antenna != 0) pcmd->antenna_mode = ENDIAN_SWAP16(antenna); else @@ -1584,7 +1679,7 @@ int mwl_fwcmd_set_aid(struct ieee80211_hw *hw, pcmd->cmd_hdr.len = ENDIAN_SWAP16(sizeof(*pcmd)); pcmd->cmd_hdr.macid = mwl_vif->macid; pcmd->aid = ENDIAN_SWAP16(aid); - memcpy(pcmd->mac_addr, bssid, ETH_ALEN); + ether_addr_copy(pcmd->mac_addr, bssid); if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_SET_AID)) { MWL_SPIN_UNLOCK(&priv->locks.fwcmd_lock); @@ -1692,7 +1787,7 @@ int mwl_fwcmd_set_edca_params(struct ieee80211_hw *hw, u8 index, pcmd->cmd_hdr.cmd = ENDIAN_SWAP16(HOSTCMD_CMD_SET_EDCA_PARAMS); pcmd->cmd_hdr.len = ENDIAN_SWAP16(sizeof(*pcmd)); - pcmd->action = ENDIAN_SWAP16(0xffff);; + pcmd->action = ENDIAN_SWAP16(0xffff); pcmd->txop = ENDIAN_SWAP16(txop); pcmd->cw_max = ENDIAN_SWAP32(ilog2(cw_max + 1)); pcmd->cw_min = ENDIAN_SWAP32(ilog2(cw_min + 1)); @@ -1700,8 +1795,8 @@ int mwl_fwcmd_set_edca_params(struct ieee80211_hw *hw, u8 index, pcmd->txq_num = index; /* The array index defined in qos.h has a reversed bk and be. - * The HW queue was not used this way; the qos code needs to be changed or - * checked + * The HW queue was not used this way; the qos code needs to + * be changed or checked */ if (index == 0) pcmd->txq_num = 1; @@ -1852,7 +1947,7 @@ int mwl_fwcmd_set_mac_addr_client(struct ieee80211_hw *hw, pcmd->cmd_hdr.len = ENDIAN_SWAP16(sizeof(*pcmd)); pcmd->cmd_hdr.macid = mwl_vif->macid; pcmd->mac_type = WL_MAC_TYPE_SECONDARY_CLIENT; - memcpy(pcmd->mac_addr, mac_addr, ETH_ALEN); + ether_addr_copy(pcmd->mac_addr, mac_addr); if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_SET_MAC_ADDR)) { MWL_SPIN_UNLOCK(&priv->locks.fwcmd_lock); @@ -1926,7 +2021,7 @@ int mwl_fwcmd_remove_mac_addr(struct ieee80211_hw *hw, pcmd->cmd_hdr.cmd = ENDIAN_SWAP16(HOSTCMD_CMD_DEL_MAC_ADDR); pcmd->cmd_hdr.len = ENDIAN_SWAP16(sizeof(*pcmd)); pcmd->cmd_hdr.macid = mwl_vif->macid; - memcpy(pcmd->mac_addr, mac_addr, ETH_ALEN); + ether_addr_copy(pcmd->mac_addr, mac_addr); if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_DEL_MAC_ADDR)) { MWL_SPIN_UNLOCK(&priv->locks.fwcmd_lock); @@ -2077,7 +2172,7 @@ int mwl_fwcmd_set_new_stn_add(struct ieee80211_hw *hw, pcmd->aid = ENDIAN_SWAP16(sta->aid); pcmd->stn_id = ENDIAN_SWAP16(sta->aid); } - memcpy(pcmd->mac_addr, sta->addr, ETH_ALEN); + ether_addr_copy(pcmd->mac_addr, sta->addr); if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ) rates = sta->supp_rates[IEEE80211_BAND_2GHZ]; @@ -2091,12 +2186,15 @@ int mwl_fwcmd_set_new_stn_add(struct ieee80211_hw *hw, pcmd->peer_info.ht_rates[2] = sta->ht_cap.mcs.rx_mask[2]; pcmd->peer_info.ht_rates[3] = sta->ht_cap.mcs.rx_mask[3]; pcmd->peer_info.ht_cap_info = ENDIAN_SWAP16(sta->ht_cap.cap); - pcmd->peer_info.mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) | + pcmd->peer_info.mac_ht_param_info = + (sta->ht_cap.ampdu_factor & 3) | ((sta->ht_cap.ampdu_density & 7) << 2); } if (sta->vht_cap.vht_supported) { - pcmd->peer_info.vht_max_rx_mcs = ENDIAN_SWAP32(*((u32 *)&sta->vht_cap.vht_mcs.rx_mcs_map)); + pcmd->peer_info.vht_max_rx_mcs = + ENDIAN_SWAP32(*((u32 *) + &sta->vht_cap.vht_mcs.rx_mcs_map)); pcmd->peer_info.vht_cap = ENDIAN_SWAP32(sta->vht_cap.cap); pcmd->peer_info.vht_rx_channel_width = sta->bandwidth; } @@ -2111,8 +2209,8 @@ int mwl_fwcmd_set_new_stn_add(struct ieee80211_hw *hw, } if (mwl_vif->is_sta == true) { - memcpy(pcmd->mac_addr, mwl_vif->sta_mac, ETH_ALEN); - + ether_addr_copy(pcmd->mac_addr, mwl_vif->sta_mac); + if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_SET_NEW_STN)) { MWL_SPIN_UNLOCK(&priv->locks.fwcmd_lock); WLDBG_EXIT_INFO(DBG_LEVEL_2, "failed execution"); @@ -2154,7 +2252,7 @@ int mwl_fwcmd_set_new_stn_add_self(struct ieee80211_hw *hw, pcmd->cmd_hdr.macid = mwl_vif->macid; pcmd->action = ENDIAN_SWAP16(HOSTCMD_ACT_STA_ACTION_ADD); - memcpy(pcmd->mac_addr, vif->addr, ETH_ALEN); + ether_addr_copy(pcmd->mac_addr, vif->addr); if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_SET_NEW_STN)) { MWL_SPIN_UNLOCK(&priv->locks.fwcmd_lock); @@ -2196,7 +2294,7 @@ int mwl_fwcmd_set_new_stn_del(struct ieee80211_hw *hw, pcmd->cmd_hdr.macid = mwl_vif->macid; pcmd->action = ENDIAN_SWAP16(HOSTCMD_ACT_STA_ACTION_REMOVE); - memcpy(pcmd->mac_addr, addr, ETH_ALEN); + ether_addr_copy(pcmd->mac_addr, addr); if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_SET_NEW_STN)) { MWL_SPIN_UNLOCK(&priv->locks.fwcmd_lock); @@ -2205,8 +2303,8 @@ int mwl_fwcmd_set_new_stn_del(struct ieee80211_hw *hw, } if (mwl_vif->is_sta == true) { - memcpy(pcmd->mac_addr, mwl_vif->sta_mac, ETH_ALEN); - + ether_addr_copy(pcmd->mac_addr, mwl_vif->sta_mac); + if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_SET_NEW_STN)) { MWL_SPIN_UNLOCK(&priv->locks.fwcmd_lock); WLDBG_EXIT_INFO(DBG_LEVEL_2, "failed execution"); @@ -2254,7 +2352,8 @@ int mwl_fwcmd_set_apmode(struct ieee80211_hw *hw, u8 apmode) } int mwl_fwcmd_update_encryption_enable(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, u8 *addr, u8 encr_type) + struct ieee80211_vif *vif, + u8 *addr, u8 encr_type) { struct mwl_priv *priv; struct mwl_vif *mwl_vif; @@ -2281,7 +2380,7 @@ int mwl_fwcmd_update_encryption_enable(struct ieee80211_hw *hw, pcmd->cmd_hdr.macid = mwl_vif->macid; pcmd->action_type = ENDIAN_SWAP32(ENCR_ACTION_ENABLE_HW_ENCR); - memcpy(pcmd->mac_addr, addr, ETH_ALEN); + ether_addr_copy(pcmd->mac_addr, addr); pcmd->action_data[0] = encr_type; if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_UPDATE_ENCRYPTION)) { @@ -2292,9 +2391,9 @@ int mwl_fwcmd_update_encryption_enable(struct ieee80211_hw *hw, if (mwl_vif->is_sta == true) { if (memcmp(mwl_vif->bssid, addr, ETH_ALEN) == 0) - memcpy(pcmd->mac_addr, mwl_vif->sta_mac, ETH_ALEN); + ether_addr_copy(pcmd->mac_addr, mwl_vif->sta_mac); else - memcpy(pcmd->mac_addr, mwl_vif->bssid, ETH_ALEN); + ether_addr_copy(pcmd->mac_addr, mwl_vif->bssid); if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_UPDATE_ENCRYPTION)) { MWL_SPIN_UNLOCK(&priv->locks.fwcmd_lock); @@ -2390,9 +2489,11 @@ int mwl_fwcmd_encryption_set_key(struct ieee80211_hw *hw, if (mwl_vif->is_sta == true) { if (memcmp(mwl_vif->bssid, addr, ETH_ALEN) == 0) - memcpy(pcmd->key_param.mac_addr, mwl_vif->sta_mac, ETH_ALEN); + ether_addr_copy(pcmd->key_param.mac_addr, + mwl_vif->sta_mac); else - memcpy(pcmd->key_param.mac_addr, mwl_vif->bssid, ETH_ALEN); + ether_addr_copy(pcmd->key_param.mac_addr, + mwl_vif->bssid); if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_UPDATE_ENCRYPTION)) { MWL_SPIN_UNLOCK(&priv->locks.fwcmd_lock); @@ -2635,7 +2736,8 @@ int mwl_fwcmd_destroy_ba(struct ieee80211_hw *hw, /* caller must hold priv->locks.stream_lock when calling the stream functions */ struct mwl_ampdu_stream *mwl_fwcmd_add_stream(struct ieee80211_hw *hw, - struct ieee80211_sta *sta, u8 tid) + struct ieee80211_sta *sta, + u8 tid) { struct mwl_priv *priv; struct mwl_ampdu_stream *stream; @@ -2673,7 +2775,7 @@ int mwl_fwcmd_start_stream(struct ieee80211_hw *hw, if (stream->state != AMPDU_STREAM_NEW) return 0; - return (ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0)); + return ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0); } void mwl_fwcmd_remove_stream(struct ieee80211_hw *hw, @@ -2904,7 +3006,7 @@ static int mwl_fwcmd_wait_complete(struct mwl_priv *priv, unsigned short cmd) { unsigned int curr_iteration = MAX_WAIT_FW_COMPLETE_ITERATIONS; - volatile unsigned short int_code = 0; + unsigned short int_code = 0; WLDBG_ENTER(DBG_LEVEL_2); @@ -2929,7 +3031,8 @@ static int mwl_fwcmd_wait_complete(struct mwl_priv *priv, unsigned short cmd) return 0; } -static int mwl_fwcmd_802_11_radio_control(struct mwl_priv *priv, bool enable, bool force) +static int mwl_fwcmd_802_11_radio_control(struct mwl_priv *priv, + bool enable, bool force) { struct hostcmd_cmd_802_11_radio_control *pcmd; unsigned long flags; @@ -3008,8 +3111,9 @@ static int mwl_fwcmd_get_tx_powers(struct mwl_priv *priv, u16 *powlist, u16 ch, return 0; } -static int mwl_fwcmd_set_tx_powers(struct mwl_priv *priv, u16 txpow[], u8 action, - u16 ch, u16 band, u16 width, u16 sub_ch) +static int mwl_fwcmd_set_tx_powers(struct mwl_priv *priv, u16 txpow[], + u8 action, u16 ch, u16 band, + u16 width, u16 sub_ch) { struct hostcmd_cmd_802_11_tx_power *pcmd; unsigned long flags; @@ -3179,38 +3283,40 @@ static void mwl_fwcmd_parse_beacon(struct mwl_priv *priv, case WLAN_EID_SUPP_RATES: case WLAN_EID_EXT_SUPP_RATES: { - int idx, basic_idx, oprate_idx; - u8 rate; + int idx, bi, oi; + u8 rate; - for (basic_idx = 0; basic_idx < SYSADPT_MAX_DATA_RATES_G; basic_idx++) { - if (beacon_info->bss_basic_rate_set[basic_idx] == 0) - break; - } - - for (oprate_idx = 0; oprate_idx < SYSADPT_MAX_DATA_RATES_G; oprate_idx++) { - if (beacon_info->op_rate_set[oprate_idx] == 0) - break; - } - - for (idx = 0; idx < elen; idx++) { - rate = pos[idx]; + for (bi = 0; bi < SYSADPT_MAX_DATA_RATES_G; + bi++) { + if (beacon_info->b_rate_set[bi] == 0) + break; + } - if ((rate & 0x80) != 0) { - if (basic_idx < SYSADPT_MAX_DATA_RATES_G) - beacon_info->bss_basic_rate_set[basic_idx++] = rate & 0x7f; - else { - elem_parse_failed = true; - break; - } - } + for (oi = 0; oi < SYSADPT_MAX_DATA_RATES_G; + oi++) { + if (beacon_info->op_rate_set[oi] == 0) + break; + } - if (oprate_idx < SYSADPT_MAX_DATA_RATES_G) - beacon_info->op_rate_set[oprate_idx++] = rate & 0x7f; + for (idx = 0; idx < elen; idx++) { + rate = pos[idx]; + if ((rate & 0x80) != 0) { + if (bi < SYSADPT_MAX_DATA_RATES_G) + beacon_info->b_rate_set[bi++] + = rate & 0x7f; else { elem_parse_failed = true; break; } } + if (oi < SYSADPT_MAX_DATA_RATES_G) + beacon_info->op_rate_set[oi++] = + rate & 0x7f; + else { + elem_parse_failed = true; + break; + } + } } break; case WLAN_EID_RSN: @@ -3222,9 +3328,9 @@ static void mwl_fwcmd_parse_beacon(struct mwl_priv *priv, case WLAN_EID_OVERLAP_BSS_SCAN_PARAM: case WLAN_EID_EXT_CAPABILITY: beacon_info->ie_ht_len += (elen + 2); - if (beacon_info->ie_ht_len > sizeof(beacon_info->ie_list_ht)) { + if (beacon_info->ie_ht_len > + sizeof(beacon_info->ie_list_ht)) { elem_parse_failed = true; - break; } else { *beacon_info->ie_ht_ptr++ = id; *beacon_info->ie_ht_ptr++ = elen; @@ -3236,9 +3342,9 @@ static void mwl_fwcmd_parse_beacon(struct mwl_priv *priv, case WLAN_EID_VHT_OPERATION: case WLAN_EID_OPMODE_NOTIF: beacon_info->ie_vht_len += (elen + 2); - if (beacon_info->ie_vht_len > sizeof(beacon_info->ie_list_vht)) { + if (beacon_info->ie_vht_len > + sizeof(beacon_info->ie_list_vht)) { elem_parse_failed = true; - break; } else { *beacon_info->ie_vht_ptr++ = id; *beacon_info->ie_vht_ptr++ = elen; @@ -3247,7 +3353,8 @@ static void mwl_fwcmd_parse_beacon(struct mwl_priv *priv, } break; case WLAN_EID_VENDOR_SPECIFIC: - if ((pos[0] == 0x00) && (pos[1] == 0x50) && (pos[2] == 0xf2)) { + if ((pos[0] == 0x00) && (pos[1] == 0x50) && + (pos[2] == 0xf2)) { if (pos[3] == 0x01) { beacon_info->ie_rsn_len = (elen + 2); beacon_info->ie_rsn_ptr = (pos - 2); @@ -3272,11 +3379,15 @@ static void mwl_fwcmd_parse_beacon(struct mwl_priv *priv, beacon_info->ie_vht_ptr = &beacon_info->ie_list_vht[0]; beacon_info->valid = true; - WLDBG_INFO(DBG_LEVEL_2, "wmm:%d, rsn:%d, rsn48:%d, ht:%d, vht:%d", - beacon_info->ie_wmm_len, beacon_info->ie_rsn_len, beacon_info->ie_rsn48_len, - beacon_info->ie_ht_len, beacon_info->ie_vht_len); + WLDBG_INFO(DBG_LEVEL_2, + "wmm:%d, rsn:%d, rsn48:%d, ht:%d, vht:%d", + beacon_info->ie_wmm_len, + beacon_info->ie_rsn_len, + beacon_info->ie_rsn48_len, + beacon_info->ie_ht_len, + beacon_info->ie_vht_len); - WLDBG_DUMP_DATA(DBG_LEVEL_2, beacon_info->bss_basic_rate_set, + WLDBG_DUMP_DATA(DBG_LEVEL_2, beacon_info->b_rate_set, SYSADPT_MAX_DATA_RATES_G); WLDBG_DUMP_DATA(DBG_LEVEL_2, beacon_info->op_rate_set, @@ -3284,8 +3395,6 @@ static void mwl_fwcmd_parse_beacon(struct mwl_priv *priv, } WLDBG_EXIT_INFO(DBG_LEVEL_2, "parse valid:%d", beacon_info->valid); - - return; } static int mwl_fwcmd_set_ies(struct mwl_priv *priv, struct mwl_vif *mwl_vif) @@ -3328,7 +3437,8 @@ static int mwl_fwcmd_set_ies(struct mwl_priv *priv, struct mwl_vif *mwl_vif) if (priv->chip_type == MWL8897) { pcmd->ie_list_len_proprietary = mwl_vif->beacon_info.ie_wmm_len; - memcpy(pcmd->ie_list_proprietary, mwl_vif->beacon_info.ie_wmm_ptr, + memcpy(pcmd->ie_list_proprietary, + mwl_vif->beacon_info.ie_wmm_ptr, pcmd->ie_list_len_proprietary); } @@ -3352,7 +3462,8 @@ einval: return -EINVAL; } -static int mwl_fwcmd_set_ap_beacon(struct mwl_priv *priv, struct mwl_vif *mwl_vif, +static int mwl_fwcmd_set_ap_beacon(struct mwl_priv *priv, + struct mwl_vif *mwl_vif, struct ieee80211_bss_conf *bss_conf) { struct hostcmd_cmd_ap_beacon *pcmd; @@ -3368,16 +3479,19 @@ static int mwl_fwcmd_set_ap_beacon(struct mwl_priv *priv, struct mwl_vif *mwl_vi if (!mwl_vif->beacon_info.valid) return -EINVAL; - /* wmm structure of start command is defined less one byte, due to following - * field country is not used, add byte one to bypass the check. + /* wmm structure of start command is defined less one byte, + * due to following field country is not used, add byte one + * to bypass the check. */ - if (mwl_vif->beacon_info.ie_wmm_len > (sizeof(pcmd->start_cmd.wmm_param) + 1)) + if (mwl_vif->beacon_info.ie_wmm_len > + (sizeof(pcmd->start_cmd.wmm_param) + 1)) goto ielenerr; if (mwl_vif->beacon_info.ie_rsn_len > sizeof(pcmd->start_cmd.rsn_ie)) goto ielenerr; - if (mwl_vif->beacon_info.ie_rsn48_len > sizeof(pcmd->start_cmd.rsn48_ie)) + if (mwl_vif->beacon_info.ie_rsn48_len > + sizeof(pcmd->start_cmd.rsn48_ie)) goto ielenerr; pcmd = (struct hostcmd_cmd_ap_beacon *)&priv->pcmd_buf[0]; @@ -3389,7 +3503,7 @@ static int mwl_fwcmd_set_ap_beacon(struct mwl_priv *priv, struct mwl_vif *mwl_vi pcmd->cmd_hdr.len = ENDIAN_SWAP16(sizeof(*pcmd)); pcmd->cmd_hdr.macid = mwl_vif->macid; - memcpy(pcmd->start_cmd.sta_mac_addr, mwl_vif->bssid, ETH_ALEN); + ether_addr_copy(pcmd->start_cmd.sta_mac_addr, mwl_vif->bssid); memcpy(pcmd->start_cmd.ssid, bss_conf->ssid, bss_conf->ssid_len); pcmd->start_cmd.bss_type = 1; pcmd->start_cmd.bcn_period = ENDIAN_SWAP16(bss_conf->beacon_int); @@ -3412,7 +3526,7 @@ static int mwl_fwcmd_set_ap_beacon(struct mwl_priv *priv, struct mwl_vif *mwl_vi memcpy(&pcmd->start_cmd.rsn48_ie, mwl_vif->beacon_info.ie_rsn48_ptr, mwl_vif->beacon_info.ie_rsn48_len); - memcpy(pcmd->start_cmd.bss_basic_rate_set, mwl_vif->beacon_info.bss_basic_rate_set, + memcpy(pcmd->start_cmd.b_rate_set, mwl_vif->beacon_info.b_rate_set, SYSADPT_MAX_DATA_RATES_G); memcpy(pcmd->start_cmd.op_rate_set, mwl_vif->beacon_info.op_rate_set, @@ -3439,7 +3553,8 @@ ielenerr: } static int mwl_fwcmd_encryption_set_cmd_info(struct hostcmd_cmd_set_key *cmd, - u8 *addr, struct ieee80211_key_conf *key) + u8 *addr, + struct ieee80211_key_conf *key) { cmd->cmd_hdr.cmd = ENDIAN_SWAP16(HOSTCMD_CMD_UPDATE_ENCRYPTION); cmd->cmd_hdr.len = ENDIAN_SWAP16(sizeof(*cmd)); @@ -3447,28 +3562,32 @@ static int mwl_fwcmd_encryption_set_cmd_info(struct hostcmd_cmd_set_key *cmd, offsetof(struct hostcmd_cmd_set_key, key_param)); cmd->key_param.key_index = ENDIAN_SWAP32(key->keyidx); cmd->key_param.key_len = ENDIAN_SWAP16(key->keylen); - memcpy(cmd->key_param.mac_addr, addr, ETH_ALEN); + ether_addr_copy(cmd->key_param.mac_addr, addr); switch (key->cipher) { case WLAN_CIPHER_SUITE_WEP40: case WLAN_CIPHER_SUITE_WEP104: cmd->key_param.key_type_id = ENDIAN_SWAP16(KEY_TYPE_ID_WEP); if (key->keyidx == 0) - cmd->key_param.key_info = ENDIAN_SWAP32(ENCR_KEY_FLAG_WEP_TXKEY); + cmd->key_param.key_info = + ENDIAN_SWAP32(ENCR_KEY_FLAG_WEP_TXKEY); break; case WLAN_CIPHER_SUITE_TKIP: cmd->key_param.key_type_id = ENDIAN_SWAP16(KEY_TYPE_ID_TKIP); - cmd->key_param.key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) - ? ENDIAN_SWAP32(ENCR_KEY_FLAG_PAIRWISE) - : ENDIAN_SWAP32(ENCR_KEY_FLAG_TXGROUPKEY); - cmd->key_param.key_info |= ENDIAN_SWAP32(ENCR_KEY_FLAG_MICKEY_VALID - | ENCR_KEY_FLAG_TSC_VALID); + cmd->key_param.key_info = + (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ? + ENDIAN_SWAP32(ENCR_KEY_FLAG_PAIRWISE) : + ENDIAN_SWAP32(ENCR_KEY_FLAG_TXGROUPKEY); + cmd->key_param.key_info |= + ENDIAN_SWAP32(ENCR_KEY_FLAG_MICKEY_VALID | + ENCR_KEY_FLAG_TSC_VALID); break; case WLAN_CIPHER_SUITE_CCMP: cmd->key_param.key_type_id = ENDIAN_SWAP16(KEY_TYPE_ID_AES); - cmd->key_param.key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) - ? ENDIAN_SWAP32(ENCR_KEY_FLAG_PAIRWISE) - : ENDIAN_SWAP32(ENCR_KEY_FLAG_TXGROUPKEY); + cmd->key_param.key_info = + (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ? + ENDIAN_SWAP32(ENCR_KEY_FLAG_PAIRWISE) : + ENDIAN_SWAP32(ENCR_KEY_FLAG_TXGROUPKEY); break; default: return -ENOTSUPP; diff --git a/mwl_fwcmd.h b/mwl_fwcmd.h index 70749b6..8fe0c13 100644 --- a/mwl_fwcmd.h +++ b/mwl_fwcmd.h @@ -102,8 +102,8 @@ int mwl_fwcmd_set_infra_mode(struct ieee80211_hw *hw, int mwl_fwcmd_set_rts_threshold(struct ieee80211_hw *hw, int threshold); -int mwl_fwcmd_set_edca_params(struct ieee80211_hw *hw, - u8 index, u16 cw_min, u16 cw_max, u8 aifs, u16 txop); +int mwl_fwcmd_set_edca_params(struct ieee80211_hw *hw, u8 index, + u16 cw_min, u16 cw_max, u8 aifs, u16 txop); int mwl_fwcmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable); @@ -142,7 +142,8 @@ int mwl_fwcmd_set_new_stn_del(struct ieee80211_hw *hw, int mwl_fwcmd_set_apmode(struct ieee80211_hw *hw, u8 apmode); int mwl_fwcmd_update_encryption_enable(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, u8 *addr, u8 encr_type); + struct ieee80211_vif *vif, + u8 *addr, u8 encr_type); int mwl_fwcmd_encryption_set_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u8 *addr, @@ -164,7 +165,8 @@ int mwl_fwcmd_destroy_ba(struct ieee80211_hw *hw, u8 idx); struct mwl_ampdu_stream *mwl_fwcmd_add_stream(struct ieee80211_hw *hw, - struct ieee80211_sta *sta, u8 tid); + struct ieee80211_sta *sta, + u8 tid); int mwl_fwcmd_start_stream(struct ieee80211_hw *hw, struct mwl_ampdu_stream *stream); diff --git a/mwl_fwdl.c b/mwl_fwdl.c index 0f1c916..6508c93 100644 --- a/mwl_fwdl.c +++ b/mwl_fwdl.c @@ -64,18 +64,21 @@ int mwl_fwdl_download_firmware(struct ieee80211_hw *hw) mwl_fwcmd_reset(hw); - /* FW before jumping to boot rom, it will enable PCIe transaction retry, wait for boot code to stop it. - */ + /* FW before jumping to boot rom, it will enable PCIe transaction retry, + * wait for boot code to stop it. + */ WL_MSEC_SLEEP(FW_CHECK_MSECS); - writel(MACREG_A2HRIC_BIT_MASK, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_CLEAR_SEL); + writel(MACREG_A2HRIC_BIT_MASK, + priv->iobase1 + MACREG_REG_A2H_INTERRUPT_CLEAR_SEL); writel(0x00, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_CAUSE); writel(0x00, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_MASK); - writel(MACREG_A2HRIC_BIT_MASK, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + writel(MACREG_A2HRIC_BIT_MASK, + priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); /* this routine interacts with SC2 bootrom to download firmware binary - * to the device. After DMA'd to SC2, the firmware could be deflated to reside - * on its respective blocks such as ITCM, DTCM, SQRAM, + * to the device. After DMA'd to SC2, the firmware could be deflated to + * reside on its respective blocks such as ITCM, DTCM, SQRAM, * (or even DDR, AFTER DDR is init'd before fw download */ WLDBG_PRINT("fw download start 88"); @@ -86,7 +89,8 @@ int mwl_fwdl_download_firmware(struct ieee80211_hw *hw) /* make sure SCRATCH2 C40 is clear, in case we are too quick */ - while (readl(priv->iobase1 + 0xc40) == 0); + while (readl(priv->iobase1 + 0xc40) == 0) + ; while (size_fw_downloaded < fw->size) { len = readl(priv->iobase1 + 0xc40); @@ -94,21 +98,24 @@ int mwl_fwdl_download_firmware(struct ieee80211_hw *hw) if (!len) break; - /* this copies the next chunk of fw binary to be delivered - */ - memcpy((char *)&priv->pcmd_buf[0], (fw->data + size_fw_downloaded), len); + /* this copies the next chunk of fw binary to be delivered */ + memcpy((char *)&priv->pcmd_buf[0], + (fw->data + size_fw_downloaded), len); /* this function writes pdata to c10, then write 2 to c18 */ mwl_fwdl_trig_pcicmd_bootcode(priv); - curr_iteration = FW_MAX_NUM_CHECKS; /* this is arbitrary per your platform; we use 0xffff */ + /* this is arbitrary per your platform; we use 0xffff */ + curr_iteration = FW_MAX_NUM_CHECKS; - /* NOTE: the following back to back checks on C1C is time sensitive, hence - * may need to be tweaked dependent on host processor. Time for SC2 to go from - * the write of event 2 to C1C == 2 is ~1300 nSec. Hence the checkings on host - * has to consider how efficient your code can be to meet this timing, or you - * can alternatively tweak this routines to fit your platform + /* NOTE: the following back to back checks on C1C is time + * sensitive, hence may need to be tweaked dependent on host + * processor. Time for SC2 to go from the write of event 2 to + * C1C == 2 is ~1300 nSec. Hence the checkings on host has to + * consider how efficient your code can be to meet this timing, + * or you can alternatively tweak this routines to fit your + * platform */ do { int_code = readl(priv->iobase1 + 0xc1c); @@ -119,16 +126,18 @@ int mwl_fwdl_download_firmware(struct ieee80211_hw *hw) do { int_code = readl(priv->iobase1 + 0xc1c); - if ((int_code & MACREG_H2ARIC_BIT_DOOR_BELL) != MACREG_H2ARIC_BIT_DOOR_BELL) + if ((int_code & MACREG_H2ARIC_BIT_DOOR_BELL) != + MACREG_H2ARIC_BIT_DOOR_BELL) break; curr_iteration--; } while (curr_iteration); if (curr_iteration == 0) { - /* This limited loop check allows you to exit gracefully without locking up - * your entire system just because fw download failed + /* This limited loop check allows you to exit gracefully + * without locking up your entire system just because fw + * download failed */ - WLDBG_PRINT("Exhausted curr_iteration during fw download"); + WLDBG_PRINT("Exhausted curr_iteration for fw download"); goto err_download; } @@ -139,9 +148,10 @@ int mwl_fwdl_download_firmware(struct ieee80211_hw *hw) (int)fw->size, size_fw_downloaded, curr_iteration); /* Now firware is downloaded successfully, so this part is to check - * whether fw can properly execute to an extent that write back signature - * to indicate its readiness to the host. NOTE: if your downloaded fw crashes, - * this signature checking will fail. This part is similar as SC1 + * whether fw can properly execute to an extent that write back + * signature to indicate its readiness to the host. NOTE: if your + * downloaded fw crashes, this signature checking will fail. This + * part is similar as SC1 */ writew(0x00, &priv->pcmd_buf[1]); mwl_fwdl_trig_pcicmd(priv); @@ -153,14 +163,15 @@ int mwl_fwdl_download_firmware(struct ieee80211_hw *hw) int_code = readl(priv->iobase1 + MACREG_REG_INT_CODE); if (!(curr_iteration % 0xff)) WLDBG_PRINT("%x;", int_code); - } while ((curr_iteration) && (int_code != HOSTCMD_SOFTAP_FWRDY_SIGNATURE)); + } while ((curr_iteration) && + (int_code != HOSTCMD_SOFTAP_FWRDY_SIGNATURE)); if (curr_iteration == 0) { - WLDBG_PRINT("Exhausted curr_iteration waiting for fw signature; firmware seems failed to operate"); + WLDBG_PRINT("Exhausted curr_iteration for fw signature"); goto err_download; } - WLDBG_PRINT("complete"); + WLDBG_PRINT("complete"); writel(0x00, priv->iobase1 + MACREG_REG_INT_CODE); WLDBG_EXIT(DBG_LEVEL_1); diff --git a/mwl_mac80211.c b/mwl_mac80211.c index f85160b..26c6286 100644 --- a/mwl_mac80211.c +++ b/mwl_mac80211.c @@ -20,6 +20,8 @@ * */ +#include + #include "mwl_sysadpt.h" #include "mwl_dev.h" #include "mwl_debug.h" @@ -116,7 +118,7 @@ static struct ieee80211_ops mwl_mac80211_ops = { .ampdu_action = mwl_mac80211_ampdu_action, }; -static irqreturn_t (*mwl_mac80211_isr)(int irq, void *dev_id) = NULL; +static irqreturn_t (*mwl_mac80211_isr)(int irq, void *dev_id); static const struct ieee80211_rate mwl_rates_24[] = { { .bitrate = 10, .hw_value = 2, }, @@ -332,7 +334,7 @@ static int mwl_mac80211_add_interface(struct ieee80211_hw *hw, mwl_vif->keyidx = 0; if (vif->type == NL80211_IFTYPE_STATION) { - memcpy(mwl_vif->sta_mac, vif->addr, ETH_ALEN); + ether_addr_copy(mwl_vif->sta_mac, vif->addr); mwl_vif->is_sta = true; mwl_fwcmd_bss_start(hw, vif, true); mwl_fwcmd_set_infra_mode(hw, vif); @@ -340,7 +342,7 @@ static int mwl_mac80211_add_interface(struct ieee80211_hw *hw, } if (vif->type == NL80211_IFTYPE_AP) { - memcpy(mwl_vif->bssid, vif->addr, ETH_ALEN); + ether_addr_copy(mwl_vif->bssid, vif->addr); mwl_fwcmd_set_new_stn_add_self(hw, vif); } @@ -391,7 +393,7 @@ static int mwl_mac80211_config(struct ieee80211_hw *hw, if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { int rate = 0; - + if (conf->chandef.chan->band == IEEE80211_BAND_2GHZ) { mwl_fwcmd_set_apmode(hw, AP_MODE_2_4GHZ_11AC_MIXED); rate = mwl_rates_24[0].hw_value; @@ -437,7 +439,8 @@ static void mwl_mac80211_bss_info_changed(struct ieee80211_hw *hw, { WLDBG_ENTER(DBG_LEVEL_5); - WLDBG_INFO(DBG_LEVEL_5, "interface: %d, change: 0x%x", vif->type, changed); + WLDBG_INFO(DBG_LEVEL_5, "interface: %d, change: 0x%x", + vif->type, changed); if (vif->type == NL80211_IFTYPE_STATION) mwl_mac80211_bss_info_changed_sta(hw, vif, info, changed); @@ -486,7 +489,7 @@ static int mwl_mac80211_set_key(struct ieee80211_hw *hw, } else { addr = sta->addr; if (mwl_vif->is_sta == true) - memcpy(mwl_vif->bssid, addr, ETH_ALEN); + ether_addr_copy(mwl_vif->bssid, addr); } if (cmd_param == SET_KEY) { @@ -732,7 +735,8 @@ static int mwl_mac80211_ampdu_action(struct ieee80211_hw *hw, SPIN_LOCK(&priv->locks.stream_lock); mwl_fwcmd_remove_stream(hw, stream); SPIN_UNLOCK(&priv->locks.stream_lock); - WLDBG_EXIT_INFO(DBG_LEVEL_5, "link is no valid now"); + WLDBG_EXIT_INFO(DBG_LEVEL_5, + "link is no valid now"); return -EBUSY; } @@ -867,7 +871,7 @@ static void mwl_mac80211_bss_info_changed_ap(struct ieee80211_hw *hw, dev_kfree_skb_any(skb); } - if ((info->ssid[0] != '\0') && + if ((info->ssid[0] != '\0') && (info->ssid_len != 0) && (!info->hidden_ssid)) mwl_fwcmd_broadcast_ssid_enable(hw, vif, true); diff --git a/mwl_main.c b/mwl_main.c index 5a81277..688613f 100644 --- a/mwl_main.c +++ b/mwl_main.c @@ -184,7 +184,7 @@ static const struct ieee80211_iface_combination ap_if_comb = { static int mwl_probe(struct pci_dev *pdev, const struct pci_device_id *id) { - static bool printed_version = false; + static bool printed_version; struct ieee80211_hw *hw; struct mwl_priv *priv; int rc = 0; @@ -339,8 +339,10 @@ static int mwl_alloc_pci_resource(struct mwl_priv *priv) if (flags & 0x04) priv->next_bar_num = 2; /* 64-bit */ - if (!request_mem_region(phys_addr, pci_resource_len(pdev, 0), MWL_DRV_NAME)) { - WLDBG_ERROR(DBG_LEVEL_0, "%s: cannot reserve PCI memory region 0", + if (!request_mem_region(phys_addr, pci_resource_len(pdev, 0), + MWL_DRV_NAME)) { + WLDBG_ERROR(DBG_LEVEL_0, + "%s: cannot reserve PCI memory region 0", MWL_DRV_NAME); goto err_reserve_mem_region_bar0; } @@ -359,13 +361,17 @@ static int mwl_alloc_pci_resource(struct mwl_priv *priv) phys_addr = pci_resource_start(pdev, priv->next_bar_num); - if (!request_mem_region(phys_addr, pci_resource_len(pdev, priv->next_bar_num), MWL_DRV_NAME)) { - WLDBG_ERROR(DBG_LEVEL_0, "%s: cannot reserve PCI memory region 1", + if (!request_mem_region(phys_addr, + pci_resource_len(pdev, priv->next_bar_num), + MWL_DRV_NAME)) { + WLDBG_ERROR(DBG_LEVEL_0, + "%s: cannot reserve PCI memory region 1", MWL_DRV_NAME); goto err_iounmap_iobase0; } - phys_addr2[0] = ioremap(phys_addr, pci_resource_len(pdev, priv->next_bar_num)); + phys_addr2[0] = ioremap(phys_addr, + pci_resource_len(pdev, priv->next_bar_num)); phys_addr2[1] = 0; priv->iobase1 = phys_addr2[0]; @@ -377,17 +383,22 @@ static int mwl_alloc_pci_resource(struct mwl_priv *priv) WLDBG_PRINT("priv->iobase1 = %x", (unsigned int)priv->iobase1); - priv->pcmd_buf = (unsigned short *) - dma_alloc_coherent(&priv->pdev->dev, CMD_BUF_SIZE, &priv->pphys_cmd_buf, GFP_KERNEL); + priv->pcmd_buf = + (unsigned short *) dma_alloc_coherent(&priv->pdev->dev, + CMD_BUF_SIZE, + &priv->pphys_cmd_buf, + GFP_KERNEL); if (priv->pcmd_buf == NULL) { - WLDBG_ERROR(DBG_LEVEL_0, "%s: cannot alloc memory for command buffer", + WLDBG_ERROR(DBG_LEVEL_0, + "%s: cannot alloc memory for command buffer", MWL_DRV_NAME); goto err_iounmap_iobase1; } WLDBG_PRINT("priv->pcmd_buf = %x priv->pphys_cmd_buf = %x", - (unsigned int)priv->pcmd_buf, (unsigned int)priv->pphys_cmd_buf); + (unsigned int)priv->pcmd_buf, + (unsigned int)priv->pphys_cmd_buf); memset(priv->pcmd_buf, 0x00, CMD_BUF_SIZE); @@ -401,7 +412,8 @@ err_iounmap_iobase1: err_release_mem_region_bar1: - release_mem_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1)); + release_mem_region(pci_resource_start(pdev, 1), + pci_resource_len(pdev, 1)); err_iounmap_iobase0: @@ -409,7 +421,8 @@ err_iounmap_iobase0: err_release_mem_region_bar0: - release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); + release_mem_region(pci_resource_start(pdev, 0), + pci_resource_len(pdev, 0)); err_reserve_mem_region_bar0: @@ -431,9 +444,13 @@ static void mwl_free_pci_resource(struct mwl_priv *priv) iounmap(priv->iobase0); iounmap(priv->iobase1); - release_mem_region(pci_resource_start(pdev, priv->next_bar_num), pci_resource_len(pdev, priv->next_bar_num)); - release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); - dma_free_coherent(&priv->pdev->dev, CMD_BUF_SIZE, priv->pcmd_buf, priv->pphys_cmd_buf); + release_mem_region(pci_resource_start(pdev, priv->next_bar_num), + pci_resource_len(pdev, + priv->next_bar_num)); + release_mem_region(pci_resource_start(pdev, 0), + pci_resource_len(pdev, 0)); + dma_free_coherent(&priv->pdev->dev, CMD_BUF_SIZE, + priv->pcmd_buf, priv->pphys_cmd_buf); WLDBG_EXIT(DBG_LEVEL_0); } @@ -458,7 +475,8 @@ static int mwl_init_firmware(struct mwl_priv *priv, char *fw_name) rc = mwl_fwdl_download_firmware(priv->hw); if (rc) { - WLDBG_ERROR(DBG_LEVEL_0, "%s: cannot download firmware image <%s>", + WLDBG_ERROR(DBG_LEVEL_0, + "%s: cannot download firmware image <%s>", MWL_DRV_NAME, fw_name); goto err_download_fw; } @@ -500,13 +518,13 @@ static void mwl_reg_notifier(struct wiphy *wiphy, if (priv->pwr_node != NULL) { for_each_property_of_node(priv->pwr_node, prop) { - if(strcmp(prop->name, "FCC") == 0) + if (strcmp(prop->name, "FCC") == 0) fcc_prop = prop; if (strcmp(prop->name, "ETSI") == 0) etsi_prop = prop; if ((prop->name[0] == request->alpha2[0]) && (prop->name[1] == request->alpha2[1])) - specific_prop = prop; + specific_prop = prop; } prop = NULL; @@ -526,27 +544,35 @@ static void mwl_reg_notifier(struct wiphy *wiphy, for (i = 0; i < SYSADPT_MAX_NUM_CHANNELS; i++) memset(&priv->tx_pwr_tbl[i], 0, sizeof(struct mwl_tx_pwr_tbl)); - + /* Load related power table */ i = 0; j = 0; while (i < prop->length) { - prop_value = be32_to_cpu(*(u32 *)(prop->value + i)); + prop_value = + be32_to_cpu(*(u32 *)(prop->value + i)); priv->tx_pwr_tbl[j].channel = prop_value; i += 4; - prop_value = be32_to_cpu(*(u32 *)(prop->value + i)); + prop_value = + be32_to_cpu(*(u32 *)(prop->value + i)); priv->tx_pwr_tbl[j].setcap = prop_value; i += 4; - for (k = 0; k < SYSADPT_TX_POWER_LEVEL_TOTAL; k++) { - prop_value = be32_to_cpu(*(u32 *)(prop->value + i)); - priv->tx_pwr_tbl[j].tx_power[k] = prop_value; + for (k = 0; k < SYSADPT_TX_POWER_LEVEL_TOTAL; + k++) { + prop_value = + be32_to_cpu(*(u32 *) + (prop->value + i)); + priv->tx_pwr_tbl[j].tx_power[k] = + prop_value; i += 4; } - prop_value = be32_to_cpu(*(u32 *)(prop->value + i)); + prop_value = + be32_to_cpu(*(u32 *)(prop->value + i)); priv->tx_pwr_tbl[j].cdd = prop_value; i += 4; - prop_value = be32_to_cpu(*(u32 *)(prop->value + i)); + prop_value = + be32_to_cpu(*(u32 *)(prop->value + i)); priv->tx_pwr_tbl[j].txantenna2 = prop_value; i += 4; j++; @@ -554,23 +580,27 @@ static void mwl_reg_notifier(struct wiphy *wiphy, /* Dump loaded power tabel */ - WLDBG_PRINT("%s: %s\n", dev_name(&wiphy->dev), prop->name); + WLDBG_PRINT("%s: %s\n", dev_name(&wiphy->dev), + prop->name); for (i = 0; i < SYSADPT_MAX_NUM_CHANNELS; i++) { + struct mwl_tx_pwr_tbl *pwr_tbl; char disp_buf[64]; char *disp_ptr; - - if (priv->tx_pwr_tbl[i].channel == 0) + + pwr_tbl = &priv->tx_pwr_tbl[i]; + if (pwr_tbl->channel == 0) break; WLDBG_PRINT("Channel: %d: 0x%x 0x%x 0x%x", - priv->tx_pwr_tbl[i].channel, - priv->tx_pwr_tbl[i].setcap, - priv->tx_pwr_tbl[i].cdd, - priv->tx_pwr_tbl[i].txantenna2); + pwr_tbl->channel, + pwr_tbl->setcap, + pwr_tbl->cdd, + pwr_tbl->txantenna2); disp_ptr = disp_buf; - for (j = 0; j < SYSADPT_TX_POWER_LEVEL_TOTAL; j++) { - disp_ptr += + for (j = 0; j < SYSADPT_TX_POWER_LEVEL_TOTAL; + j++) { + disp_ptr += sprintf(disp_ptr, "%x ", - priv->tx_pwr_tbl[i].tx_power[j]); + pwr_tbl->tx_power[j]); } WLDBG_PRINT("%s", disp_buf); } @@ -601,7 +631,7 @@ static int mwl_process_of_dts(struct mwl_priv *priv) return -EPERM; /* look for all matching property names - */ + */ for_each_property_of_node(priv->dt_node, prop) { if (strcmp(prop->name, "marvell,2ghz") == 0) priv->disable_2g = true; @@ -721,8 +751,10 @@ static void mwl_set_caps(struct mwl_priv *priv) /* set up band information for 2.4G */ if (priv->disable_2g == false) { - BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl_channels_24)); - memcpy(priv->channels_24, mwl_channels_24, sizeof(mwl_channels_24)); + BUILD_BUG_ON(sizeof(priv->channels_24) != + sizeof(mwl_channels_24)); + memcpy(priv->channels_24, mwl_channels_24, + sizeof(mwl_channels_24)); BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl_rates_24)); memcpy(priv->rates_24, mwl_rates_24, sizeof(mwl_rates_24)); @@ -742,8 +774,10 @@ static void mwl_set_caps(struct mwl_priv *priv) /* set up band information for 5G */ if (priv->disable_5g == false) { - BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl_channels_50)); - memcpy(priv->channels_50, mwl_channels_50, sizeof(mwl_channels_50)); + BUILD_BUG_ON(sizeof(priv->channels_50) != + sizeof(mwl_channels_50)); + memcpy(priv->channels_50, mwl_channels_50, + sizeof(mwl_channels_50)); BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl_rates_50)); memcpy(priv->rates_50, mwl_rates_50, sizeof(mwl_rates_50)); @@ -972,16 +1006,19 @@ static void mwl_watchdog_ba_events(struct work_struct *work) SPIN_LOCK(&priv->locks.stream_lock); } } else { - for (stream_index = 0; stream_index < SYSADPT_TX_AMPDU_QUEUES; stream_index++) { + for (stream_index = 0; + stream_index < SYSADPT_TX_AMPDU_QUEUES; + stream_index++) { streams = &priv->ampdu[stream_index]; - if (streams->state == AMPDU_STREAM_ACTIVE) { - ieee80211_stop_tx_ba_session(streams->sta, - streams->tid); - SPIN_UNLOCK(&priv->locks.stream_lock); - mwl_fwcmd_destroy_ba(hw, stream_index); - SPIN_LOCK(&priv->locks.stream_lock); - } + if (streams->state != AMPDU_STREAM_ACTIVE) + continue; + + ieee80211_stop_tx_ba_session(streams->sta, + streams->tid); + SPIN_UNLOCK(&priv->locks.stream_lock); + mwl_fwcmd_destroy_ba(hw, stream_index); + SPIN_LOCK(&priv->locks.stream_lock); } } } @@ -993,14 +1030,13 @@ done: status = readl(priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); writel(status | MACREG_A2HRIC_BA_WATCHDOG, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); - - return; } static irqreturn_t mwl_interrupt(int irq, void *dev_id) { struct ieee80211_hw *hw = dev_id; struct mwl_priv *priv; + void *int_status_mask; unsigned int int_status, clr_status; u32 status; @@ -1008,6 +1044,8 @@ static irqreturn_t mwl_interrupt(int irq, void *dev_id) priv = hw->priv; BUG_ON(!priv); + int_status_mask = priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK; + int_status = readl(priv->iobase1 + MACREG_REG_A2H_INTERRUPT_CAUSE); if (int_status == 0x00000000) @@ -1022,9 +1060,9 @@ static irqreturn_t mwl_interrupt(int irq, void *dev_id) int_status &= ~MACREG_A2HRIC_BIT_TX_DONE; if (priv->is_tx_schedule == false) { - status = readl(priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + status = readl(int_status_mask); writel((status & ~MACREG_A2HRIC_BIT_TX_DONE), - priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + int_status_mask); tasklet_schedule(&priv->tx_task); priv->is_tx_schedule = true; } @@ -1034,18 +1072,18 @@ static irqreturn_t mwl_interrupt(int irq, void *dev_id) int_status &= ~MACREG_A2HRIC_BIT_RX_RDY; if (priv->is_rx_schedule == false) { - status = readl(priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + status = readl(int_status_mask); writel((status & ~MACREG_A2HRIC_BIT_RX_RDY), - priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + int_status_mask); tasklet_schedule(&priv->rx_task); priv->is_rx_schedule = true; } } if (int_status & MACREG_A2HRIC_BA_WATCHDOG) { - status = readl(priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + status = readl(int_status_mask); writel((status & ~MACREG_A2HRIC_BA_WATCHDOG), - priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + int_status_mask); int_status &= ~MACREG_A2HRIC_BA_WATCHDOG; ieee80211_queue_work(hw, &priv->watchdog_ba_handle); } diff --git a/mwl_rx.c b/mwl_rx.c index c8abaea..5660070 100644 --- a/mwl_rx.c +++ b/mwl_rx.c @@ -30,7 +30,8 @@ /* CONSTANTS AND MACROS */ -#define MAX_NUM_RX_RING_BYTES SYSADPT_MAX_NUM_RX_DESC * sizeof(struct mwl_rx_desc) +#define MAX_NUM_RX_RING_BYTES (SYSADPT_MAX_NUM_RX_DESC * \ + sizeof(struct mwl_rx_desc)) #define FIRST_RXD priv->desc_data[0].prx_ring[0] #define CURR_RXD priv->desc_data[0].prx_ring[curr_desc] @@ -68,7 +69,8 @@ static void mwl_rx_ring_cleanup(struct mwl_priv *priv); static void mwl_rx_ring_free(struct mwl_priv *priv); static inline void mwl_rx_prepare_status(struct mwl_rx_desc *pdesc, struct ieee80211_rx_status *status); -static inline struct mwl_vif *mwl_rx_find_vif_bss(struct list_head *vif_list, u8 *bssid); +static inline struct mwl_vif *mwl_rx_find_vif_bss(struct list_head *vif_list, + u8 *bssid); static inline void mwl_rx_remove_dma_header(struct sk_buff *skb, u16 qos); static int mwl_rx_refill(struct mwl_priv *priv, struct mwl_rx_desc *pdesc); @@ -93,7 +95,8 @@ int mwl_rx_init(struct ieee80211_hw *hw) rc = mwl_rx_ring_init(priv); if (rc) { mwl_rx_ring_free(priv); - WLDBG_ERROR(DBG_LEVEL_4, "initializing RX ring failed"); + WLDBG_ERROR(DBG_LEVEL_4, + "initializing RX ring failed"); } } @@ -140,7 +143,8 @@ void mwl_rx_recv(unsigned long data) curr_desc = priv->desc_data[0].pnext_rx_desc; if (curr_desc == NULL) { - status_mask = readl(priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + status_mask = readl(priv->iobase1 + + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); writel(status_mask | MACREG_A2HRIC_BIT_RX_RDY, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); @@ -162,8 +166,9 @@ void mwl_rx_recv(unsigned long data) pkt_len = curr_desc->pkt_len; if (skb_tailroom(prx_skb) < pkt_len) { - WLDBG_PRINT("Critical error: not enough tail room =%x pkt_len=%x, curr_desc=%x, curr_desc_data=%x", - skb_tailroom(prx_skb), pkt_len, curr_desc, curr_desc->pbuff_data); + WLDBG_PRINT("Critical error: %x %x %x %x", + skb_tailroom(prx_skb), pkt_len, + curr_desc, curr_desc->pbuff_data); dev_kfree_skb_any(prx_skb); goto out; } @@ -209,7 +214,8 @@ void mwl_rx_recv(unsigned long data) if (status.flag & RX_FLAG_MMIC_ERROR) { struct mwl_dma_data *tr; - tr = (struct mwl_dma_data *)prx_skb->data; + tr = (struct mwl_dma_data *) + prx_skb->data; memset((void *)&(tr->data), 0, 4); pkt_len += 4; } @@ -235,7 +241,8 @@ out: priv->desc_data[0].pnext_rx_desc = curr_desc; - status_mask = readl(priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + status_mask = readl(priv->iobase1 + + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); writel(status_mask | MACREG_A2HRIC_BIT_RX_RDY, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); @@ -255,10 +262,11 @@ static int mwl_rx_ring_alloc(struct mwl_priv *priv) BUG_ON(!priv); priv->desc_data[0].prx_ring = - (struct mwl_rx_desc *)dma_alloc_coherent(&priv->pdev->dev, - MAX_NUM_RX_RING_BYTES, - &priv->desc_data[0].pphys_rx_ring, - GFP_KERNEL); + (struct mwl_rx_desc *) + dma_alloc_coherent(&priv->pdev->dev, + MAX_NUM_RX_RING_BYTES, + &priv->desc_data[0].pphys_rx_ring, + GFP_KERNEL); if (priv->desc_data[0].prx_ring == NULL) { WLDBG_ERROR(DBG_LEVEL_4, "can not alloc mem"); @@ -269,7 +277,8 @@ static int mwl_rx_ring_alloc(struct mwl_priv *priv) memset(priv->desc_data[0].prx_ring, 0x00, MAX_NUM_RX_RING_BYTES); WLDBG_EXIT_INFO(DBG_LEVEL_4, "RX ring vaddr: 0x%x paddr: 0x%x", - priv->desc_data[0].prx_ring, priv->desc_data[0].pphys_rx_ring); + priv->desc_data[0].prx_ring, + priv->desc_data[0].pphys_rx_ring); return 0; } @@ -277,23 +286,32 @@ static int mwl_rx_ring_alloc(struct mwl_priv *priv) static int mwl_rx_ring_init(struct mwl_priv *priv) { int curr_desc; + struct mwl_desc_data *desc; - WLDBG_ENTER_INFO(DBG_LEVEL_4, "initializing %i descriptors", SYSADPT_MAX_NUM_RX_DESC); + WLDBG_ENTER_INFO(DBG_LEVEL_4, "initializing %i descriptors", + SYSADPT_MAX_NUM_RX_DESC); - if (priv->desc_data[0].prx_ring != NULL) { - priv->desc_data[0].rx_buf_size = SYSADPT_MAX_AGGR_SIZE; + desc = &priv->desc_data[0]; + + if (desc->prx_ring != NULL) { + desc->rx_buf_size = SYSADPT_MAX_AGGR_SIZE; - for (curr_desc = 0; curr_desc < SYSADPT_MAX_NUM_RX_DESC; curr_desc++) { - CURR_RXD.psk_buff = dev_alloc_skb(priv->desc_data[0].rx_buf_size); + for (curr_desc = 0; curr_desc < SYSADPT_MAX_NUM_RX_DESC; + curr_desc++) { + CURR_RXD.psk_buff = + dev_alloc_skb(desc->rx_buf_size); if (skb_linearize(CURR_RXD.psk_buff)) { dev_kfree_skb_any(CURR_RXD.psk_buff); - WLDBG_ERROR(DBG_LEVEL_4, "need linearize memory"); - WLDBG_EXIT_INFO(DBG_LEVEL_4, "no suitable memory"); + WLDBG_ERROR(DBG_LEVEL_4, + "need linearize memory"); + WLDBG_EXIT_INFO(DBG_LEVEL_4, + "no suitable memory"); return -ENOMEM; } - skb_reserve(CURR_RXD.psk_buff, SYSADPT_MIN_BYTES_HEADROOM); + skb_reserve(CURR_RXD.psk_buff, + SYSADPT_MIN_BYTES_HEADROOM); CURR_RXD.rx_control = EAGLE_RXD_CTRL_DRIVER_OWN; CURR_RXD.status = EAGLE_RXD_STATUS_OK; CURR_RXD.qos_ctrl = 0x0000; @@ -301,40 +319,54 @@ static int mwl_rx_ring_init(struct mwl_priv *priv) CURR_RXD.rssi = 0x00; if (CURR_RXD.psk_buff != NULL) { + dma_addr_t dma; + u32 val; + CURR_RXD.pkt_len = SYSADPT_MAX_AGGR_SIZE; CURR_RXD.pbuff_data = CURR_RXD.psk_buff->data; + dma = pci_map_single(priv->pdev, + CURR_RXD.psk_buff->data, + desc->rx_buf_size, + PCI_DMA_FROMDEVICE); CURR_RXD.pphys_buff_data = - ENDIAN_SWAP32(pci_map_single(priv->pdev, - CURR_RXD.psk_buff->data, - priv->desc_data[0].rx_buf_size, - PCI_DMA_FROMDEVICE)); + ENDIAN_SWAP32(dma); CURR_RXD.pnext = &NEXT_RXD; + val = (u32)desc->pphys_rx_ring + + ((curr_desc + 1) * + sizeof(struct mwl_rx_desc)); CURR_RXD.pphys_next = - ENDIAN_SWAP32((u32)priv->desc_data[0].pphys_rx_ring + - ((curr_desc + 1) * sizeof(struct mwl_rx_desc))); + ENDIAN_SWAP32(val); WLDBG_INFO(DBG_LEVEL_4, - "rxdesc: %i status: 0x%x (%i) len: 0x%x (%i)", - curr_desc, EAGLE_TXD_STATUS_IDLE, EAGLE_TXD_STATUS_IDLE, - priv->desc_data[0].rx_buf_size, priv->desc_data[0].rx_buf_size); + "rxdesc:%i 0x%x(%i) 0x%x(%i)", + curr_desc, + EAGLE_TXD_STATUS_IDLE, + EAGLE_TXD_STATUS_IDLE, + desc->rx_buf_size, + desc->rx_buf_size); WLDBG_INFO(DBG_LEVEL_4, - "rxdesc: %i vnext: 0x%p pnext: 0x%x", curr_desc, - CURR_RXD.pnext, ENDIAN_SWAP32(CURR_RXD.pphys_next)); + "rxdesc: %i vnext: 0x%p pnext: 0x%x", + curr_desc, + CURR_RXD.pnext, + ENDIAN_SWAP32(CURR_RXD.pphys_next)); } else { WLDBG_ERROR(DBG_LEVEL_4, - "rxdesc %i: no skbuff available", curr_desc); - WLDBG_EXIT_INFO(DBG_LEVEL_4, "no socket buffer"); + "rxdesc %i: no skbuff available", + curr_desc); + WLDBG_EXIT_INFO(DBG_LEVEL_4, + "no socket buffer"); return -ENOMEM; } } LAST_RXD.pphys_next = - ENDIAN_SWAP32((u32)priv->desc_data[0].pphys_rx_ring); + ENDIAN_SWAP32((u32)desc->pphys_rx_ring); LAST_RXD.pnext = &FIRST_RXD; priv->desc_data[0].pnext_rx_desc = &FIRST_RXD; WLDBG_EXIT_INFO(DBG_LEVEL_4, - "last rxdesc vnext: 0x%p pnext: 0x%x vfirst 0x%x", - LAST_RXD.pnext, ENDIAN_SWAP32(LAST_RXD.pphys_next), - priv->desc_data[0].pnext_rx_desc); + "last rxdesc vnext:0x%p pnext:0x%x vfirst 0x%x", + LAST_RXD.pnext, + ENDIAN_SWAP32(LAST_RXD.pphys_next), + desc->pnext_rx_desc); return 0; } @@ -354,30 +386,33 @@ static void mwl_rx_ring_cleanup(struct mwl_priv *priv) BUG_ON(!priv); if (priv->desc_data[0].prx_ring != NULL) { - for (curr_desc = 0; curr_desc < SYSADPT_MAX_NUM_RX_DESC; curr_desc++) { - if (CURR_RXD.psk_buff != NULL) { - if (skb_shinfo(CURR_RXD.psk_buff)->nr_frags) - skb_shinfo(CURR_RXD.psk_buff)->nr_frags = 0; + for (curr_desc = 0; curr_desc < SYSADPT_MAX_NUM_RX_DESC; + curr_desc++) { + if (CURR_RXD.psk_buff == NULL) + continue; - if (skb_shinfo(CURR_RXD.psk_buff)->frag_list) - skb_shinfo(CURR_RXD.psk_buff)->frag_list = NULL; + if (skb_shinfo(CURR_RXD.psk_buff)->nr_frags) + skb_shinfo(CURR_RXD.psk_buff)->nr_frags = 0; - pci_unmap_single(priv->pdev, - ENDIAN_SWAP32(CURR_RXD.pphys_buff_data), - priv->desc_data[0].rx_buf_size, - PCI_DMA_FROMDEVICE); + if (skb_shinfo(CURR_RXD.psk_buff)->frag_list) + skb_shinfo(CURR_RXD.psk_buff)->frag_list = NULL; - dev_kfree_skb_any(CURR_RXD.psk_buff); + pci_unmap_single(priv->pdev, + ENDIAN_SWAP32 + (CURR_RXD.pphys_buff_data), + priv->desc_data[0].rx_buf_size, + PCI_DMA_FROMDEVICE); - WLDBG_INFO(DBG_LEVEL_4, - "unmapped+free'd rxdesc %i vaddr: 0x%p paddr: 0x%x len: %i", - curr_desc, CURR_RXD.pbuff_data, - ENDIAN_SWAP32(CURR_RXD.pphys_buff_data), - priv->desc_data[0].rx_buf_size); + dev_kfree_skb_any(CURR_RXD.psk_buff); - CURR_RXD.pbuff_data = NULL; - CURR_RXD.psk_buff = NULL; - } + WLDBG_INFO(DBG_LEVEL_4, + "unmapped+free'd %i 0x%p 0x%x %i", + curr_desc, CURR_RXD.pbuff_data, + ENDIAN_SWAP32(CURR_RXD.pphys_buff_data), + priv->desc_data[0].rx_buf_size); + + CURR_RXD.pbuff_data = NULL; + CURR_RXD.psk_buff = NULL; } } @@ -416,7 +451,7 @@ static inline void mwl_rx_prepare_status(struct mwl_rx_desc *pdesc, memset(status, 0, sizeof(*status)); - status->signal = -(pdesc->rssi + W836X_RSSI_OFFSET); + status->signal = -(pdesc->rssi + W836X_RSSI_OFFSET); switch (pdesc->rate.format) { case RX_RATE_INFO_FORMAT_11N: @@ -460,15 +495,18 @@ static inline void mwl_rx_prepare_status(struct mwl_rx_desc *pdesc, status->freq = ieee80211_channel_to_frequency(pdesc->channel, status->band); - /* check if status has a specific error bit (bit 7)set or indicates a general decrypt error - */ - if ((pdesc->status == GENERAL_DECRYPT_ERR) || (pdesc->status & DECRYPT_ERR_MASK)) { + /* check if status has a specific error bit (bit 7) set or indicates + * a general decrypt error + */ + if ((pdesc->status == GENERAL_DECRYPT_ERR) || + (pdesc->status & DECRYPT_ERR_MASK)) { /* check if status is not equal to 0xFF * the 0xFF check is for backward compatibility */ if (pdesc->status != GENERAL_DECRYPT_ERR) { - if (((pdesc->status & (~DECRYPT_ERR_MASK)) & TKIP_DECRYPT_MIC_ERR) && - !((pdesc->status & (WEP_DECRYPT_ICV_ERR | TKIP_DECRYPT_ICV_ERR)))) { + if (((pdesc->status & (~DECRYPT_ERR_MASK)) & + TKIP_DECRYPT_MIC_ERR) && !((pdesc->status & + (WEP_DECRYPT_ICV_ERR | TKIP_DECRYPT_ICV_ERR)))) { status->flag |= RX_FLAG_MMIC_ERROR; } } @@ -477,7 +515,8 @@ static inline void mwl_rx_prepare_status(struct mwl_rx_desc *pdesc, WLDBG_EXIT(DBG_LEVEL_4); } -static inline struct mwl_vif *mwl_rx_find_vif_bss(struct list_head *vif_list, u8 *bssid) +static inline struct mwl_vif *mwl_rx_find_vif_bss(struct list_head *vif_list, + u8 *bssid) { struct mwl_vif *mwl_vif; diff --git a/mwl_sysadpt.h b/mwl_sysadpt.h index a066931..222e559 100644 --- a/mwl_sysadpt.h +++ b/mwl_sysadpt.h @@ -38,9 +38,11 @@ #define SYSADPT_NUM_OF_AP 16 -#define SYSADPT_TOTAL_TX_QUEUES (SYSADPT_TX_WMM_QUEUES + SYSADPT_NUM_OF_AP) +#define SYSADPT_TOTAL_TX_QUEUES (SYSADPT_TX_WMM_QUEUES + \ + SYSADPT_NUM_OF_AP) -#define SYSADPT_TOTAL_HW_QUEUES (SYSADPT_TX_WMM_QUEUES + SYSADPT_TX_AMPDU_QUEUES) +#define SYSADPT_TOTAL_HW_QUEUES (SYSADPT_TX_WMM_QUEUES + \ + SYSADPT_TX_AMPDU_QUEUES) #define SYSADPT_NUM_OF_DESC_DATA (4 + SYSADPT_NUM_OF_AP) diff --git a/mwl_tx.c b/mwl_tx.c index 157bc01..150d412 100644 --- a/mwl_tx.c +++ b/mwl_tx.c @@ -32,7 +32,8 @@ /* CONSTANTS AND MACROS */ -#define MAX_NUM_TX_RING_BYTES (SYSADPT_MAX_NUM_TX_DESC * sizeof(struct mwl_tx_desc)) +#define MAX_NUM_TX_RING_BYTES (SYSADPT_MAX_NUM_TX_DESC * \ + sizeof(struct mwl_tx_desc)) #define FIRST_TXD(i) priv->desc_data[i].ptx_ring[0] #define CURR_TXD(i) priv->desc_data[i].ptx_ring[curr_desc] @@ -48,7 +49,12 @@ #define MWL_QOS_ACK_POLICY_BLOCKACK 0x0060 #define EXT_IV 0x20 -#define INCREASE_IV(iv16, iv32) {(iv16)++; if ((iv16) == 0) (iv32)++; } +#define INCREASE_IV(iv16, iv32) \ +{ \ + (iv16)++; \ + if ((iv16) == 0) \ + (iv32)++; \ +} /* Transmit rate information constants */ @@ -71,7 +77,9 @@ static int mwl_tx_ring_init(struct mwl_priv *priv); static void mwl_tx_ring_cleanup(struct mwl_priv *priv); static void mwl_tx_ring_free(struct mwl_priv *priv); static inline void mwl_tx_add_dma_header(struct mwl_priv *priv, - struct sk_buff *skb, int head_pad, int tail_pad); + struct sk_buff *skb, + int head_pad, + int tail_pad); static inline void mwl_tx_encapsulate_frame(struct mwl_priv *priv, struct sk_buff *skb, bool *ccmp); static inline void mwl_tx_insert_ccmp_hdr(u8 *pccmp_hdr, @@ -95,7 +103,7 @@ int mwl_tx_init(struct ieee80211_hw *hw) priv = hw->priv; BUG_ON(!priv); - skb_queue_head_init(&priv->delay_freeq); + skb_queue_head_init(&priv->delay_q); rc = mwl_tx_ring_alloc(priv); if (rc) { @@ -123,7 +131,7 @@ void mwl_tx_deinit(struct ieee80211_hw *hw) priv = hw->priv; BUG_ON(!priv); - skb_queue_purge(&priv->delay_freeq); + skb_queue_purge(&priv->delay_q); mwl_tx_ring_cleanup(priv); mwl_tx_ring_free(priv); @@ -150,6 +158,7 @@ void mwl_tx_xmit(struct ieee80211_hw *hw, struct ieee80211_mgmt *mgmt; bool eapol_frame = false; bool ccmp = false; + struct mwl_dma_data *dma_data; struct mwl_tx_ctrl *tx_ctrl; WLDBG_ENTER(DBG_LEVEL_3); @@ -179,7 +188,8 @@ void mwl_tx_xmit(struct ieee80211_hw *hw, mwl_tx_encapsulate_frame(priv, skb, &ccmp); - wh = &((struct mwl_dma_data *)skb->data)->wh; + dma_data = (struct mwl_dma_data *)skb->data; + wh = &dma_data->wh; tx_info = IEEE80211_SKB_CB(skb); mwl_vif = MWL_VIF(tx_info->control.vif); @@ -211,7 +221,7 @@ void mwl_tx_xmit(struct ieee80211_hw *hw, xmitcontrol |= EAGLE_TXD_XMITCTRL_USE_MC_RATE; if (ccmp) { - mwl_tx_insert_ccmp_hdr(((struct mwl_dma_data *)skb->data)->data, + mwl_tx_insert_ccmp_hdr(dma_data->data, mwl_vif->keyidx, mwl_vif->iv16, mwl_vif->iv32); @@ -220,18 +230,21 @@ void mwl_tx_xmit(struct ieee80211_hw *hw, } else { if (ccmp) { if (mwl_vif->is_sta == true) { - mwl_tx_insert_ccmp_hdr(((struct mwl_dma_data *)skb->data)->data, + mwl_tx_insert_ccmp_hdr(dma_data->data, mwl_vif->keyidx, mwl_vif->iv16, mwl_vif->iv32); - INCREASE_IV(mwl_vif->iv16, mwl_vif->iv32); + INCREASE_IV(mwl_vif->iv16, + mwl_vif->iv32); } else { struct mwl_sta *sta_info = MWL_STA(sta); - mwl_tx_insert_ccmp_hdr(((struct mwl_dma_data *)skb->data)->data, - 0, sta_info->iv16, + mwl_tx_insert_ccmp_hdr(dma_data->data, + 0, + sta_info->iv16, sta_info->iv32); - INCREASE_IV(sta_info->iv16, sta_info->iv32); + INCREASE_IV(sta_info->iv16, + sta_info->iv32); } } } @@ -248,9 +261,11 @@ void mwl_tx_xmit(struct ieee80211_hw *hw, */ if (mgmtframe) { if (unlikely(ieee80211_is_action(wh->frame_control) && - mgmt->u.action.category == WLAN_CATEGORY_BACK && - mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ)) { - u16 capab = ENDIAN_SWAP16(mgmt->u.action.u.addba_req.capab); + mgmt->u.action.category == WLAN_CATEGORY_BACK && + mgmt->u.action.u.addba_req.action_code == + WLAN_ACTION_ADDBA_REQ)) { + u16 capab = + ENDIAN_SWAP16(mgmt->u.action.u.addba_req.capab); tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2; index = mwl_tx_tid_queue_mapping(tid); } @@ -270,7 +285,8 @@ void mwl_tx_xmit(struct ieee80211_hw *hw, if (stream->state == AMPDU_STREAM_ACTIVE) { WARN_ON(!(qos & MWL_QOS_ACK_POLICY_BLOCKACK)); - txpriority = (SYSADPT_TX_WMM_QUEUES + stream->idx) % + txpriority = + (SYSADPT_TX_WMM_QUEUES + stream->idx) % SYSADPT_TOTAL_HW_QUEUES; } else if (stream->state == AMPDU_STREAM_NEW) { /* We get here if the driver sends us packets @@ -294,8 +310,7 @@ void mwl_tx_xmit(struct ieee80211_hw *hw, * case, so this is really just a safety check. */ WLDBG_WARNING(DBG_LEVEL_3, - "cannot send packet while ADDBA " - "dialog is underway."); + "can't send packet during ADDBA"); SPIN_UNLOCK(&priv->locks.stream_lock); dev_kfree_skb_any(skb); return; @@ -357,6 +372,9 @@ void mwl_tx_done(unsigned long data) int num; struct sk_buff *done_skb; struct mwl_rate_info rate_info; + struct mwl_dma_data *tr; + struct ieee80211_tx_info *info; + int hdrlen; WLDBG_ENTER(DBG_LEVEL_3); @@ -368,8 +386,10 @@ void mwl_tx_done(unsigned long data) for (num = 0; num < SYSADPT_NUM_OF_DESC_DATA; num++) { while (STALE_TXD(num) - && (STALE_TXD(num)->status & ENDIAN_SWAP32(EAGLE_TXD_STATUS_OK)) - && (!(STALE_TXD(num)->status & ENDIAN_SWAP32(EAGLE_TXD_STATUS_FW_OWNED)))) { + && (STALE_TXD(num)->status & + ENDIAN_SWAP32(EAGLE_TXD_STATUS_OK)) + && (!(STALE_TXD(num)->status & + ENDIAN_SWAP32(EAGLE_TXD_STATUS_FW_OWNED)))) { pci_unmap_single(priv->pdev, ENDIAN_SWAP32(STALE_TXD(num)->pkt_ptr), STALE_TXD(num)->psk_buff->len, @@ -378,69 +398,66 @@ void mwl_tx_done(unsigned long data) rate_info = STALE_TXD(num)->rate_info; STALE_TXD(num)->pkt_len = 0; STALE_TXD(num)->psk_buff = NULL; - STALE_TXD(num)->status = ENDIAN_SWAP32(EAGLE_TXD_STATUS_IDLE); + STALE_TXD(num)->status = + ENDIAN_SWAP32(EAGLE_TXD_STATUS_IDLE); priv->fw_desc_cnt[num]--; STALE_TXD(num) = STALE_TXD(num)->pnext; - wmb(); - - { - struct mwl_dma_data *tr; - struct ieee80211_tx_info *info; - int hdrlen; - - tr = (struct mwl_dma_data *)done_skb->data; - info = IEEE80211_SKB_CB(done_skb); - ieee80211_tx_info_clear_status(info); - - info->status.rates[0].idx = -1; - - if (ieee80211_is_data(tr->wh.frame_control) || - ieee80211_is_data_qos(tr->wh.frame_control)) { - skb_get(done_skb); - skb_queue_tail(&priv->delay_freeq, done_skb); - - if (skb_queue_len(&priv->delay_freeq) > SYSADPT_DELAY_FREE_Q_LIMIT) - dev_kfree_skb_any(skb_dequeue(&priv->delay_freeq)); - - /* Prepare rate information - */ - info->status.rates[0].idx = rate_info.rate_id_mcs; - if (rate_info.format == TX_RATE_FORMAT_LEGACY){ - if (hw->conf.chandef.chan->hw_value > - BAND_24_CHANNEL_NUM) { - info->status.rates[0].idx -= 5; - } - } - if (rate_info.format == TX_RATE_FORMAT_11N) - info->status.rates[0].flags |= - IEEE80211_TX_RC_MCS; - if (rate_info.format == TX_RATE_FORMAT_11AC) - info->status.rates[0].flags |= - IEEE80211_TX_RC_VHT_MCS; - if (rate_info.bandwidth == TX_RATE_BANDWIDTH_40) - info->status.rates[0].flags |= - IEEE80211_TX_RC_40_MHZ_WIDTH; - if (rate_info.bandwidth == TX_RATE_BANDWIDTH_80) - info->status.rates[0].flags |= - IEEE80211_TX_RC_80_MHZ_WIDTH; - if (rate_info.short_gi == TX_RATE_INFO_SHORT_GI) - info->status.rates[0].flags |= - IEEE80211_TX_RC_SHORT_GI; - info->status.rates[0].count = 1; - - info->status.rates[1].idx = -1; - } + wmb(); /* memory barrier */ - /* Remove H/W dma header - */ - hdrlen = ieee80211_hdrlen(tr->wh.frame_control); - memmove(tr->data - hdrlen, &tr->wh, hdrlen); - skb_pull(done_skb, sizeof(*tr) - hdrlen); + tr = (struct mwl_dma_data *)done_skb->data; + info = IEEE80211_SKB_CB(done_skb); + ieee80211_tx_info_clear_status(info); + + info->status.rates[0].idx = -1; - info->flags |= IEEE80211_TX_STAT_ACK; + if (ieee80211_is_data(tr->wh.frame_control) || + ieee80211_is_data_qos(tr->wh.frame_control)) { + skb_get(done_skb); + skb_queue_tail(&priv->delay_q, done_skb); - ieee80211_tx_status(hw, done_skb); + if (skb_queue_len(&priv->delay_q) > + SYSADPT_DELAY_FREE_Q_LIMIT) + dev_kfree_skb_any( + skb_dequeue(&priv->delay_q)); + + /* Prepare rate information + */ + info->status.rates[0].idx = + rate_info.rate_id_mcs; + if (rate_info.format == TX_RATE_FORMAT_LEGACY) { + if (hw->conf.chandef.chan->hw_value > + BAND_24_CHANNEL_NUM) { + info->status.rates[0].idx -= 5; + } + } + if (rate_info.format == TX_RATE_FORMAT_11N) + info->status.rates[0].flags |= + IEEE80211_TX_RC_MCS; + if (rate_info.format == TX_RATE_FORMAT_11AC) + info->status.rates[0].flags |= + IEEE80211_TX_RC_VHT_MCS; + if (rate_info.bandwidth == TX_RATE_BANDWIDTH_40) + info->status.rates[0].flags |= + IEEE80211_TX_RC_40_MHZ_WIDTH; + if (rate_info.bandwidth == TX_RATE_BANDWIDTH_80) + info->status.rates[0].flags |= + IEEE80211_TX_RC_80_MHZ_WIDTH; + if (rate_info.short_gi == TX_RATE_INFO_SHORT_GI) + info->status.rates[0].flags |= + IEEE80211_TX_RC_SHORT_GI; + info->status.rates[0].count = 1; + + info->status.rates[1].idx = -1; } + + /* Remove H/W dma header + */ + hdrlen = ieee80211_hdrlen(tr->wh.frame_control); + memmove(tr->data - hdrlen, &tr->wh, hdrlen); + skb_pull(done_skb, sizeof(*tr) - hdrlen); + + info->flags |= IEEE80211_TX_STAT_ACK; + ieee80211_tx_status(hw, done_skb); } } @@ -449,7 +466,8 @@ void mwl_tx_done(unsigned long data) if (priv->irq != -1) { u32 status; - status = readl(priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); + status = readl(priv->iobase1 + + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); writel(status | MACREG_A2HRIC_BIT_TX_DONE, priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK); @@ -487,16 +505,19 @@ static int mwl_tx_ring_alloc(struct mwl_priv *priv) WLDBG_INFO(DBG_LEVEL_3, "allocating %i (0x%x) bytes", MAX_NUM_TX_RING_BYTES, MAX_NUM_TX_RING_BYTES); - priv->desc_data[num].ptx_ring = - (struct mwl_tx_desc *) (mem + num * MAX_NUM_TX_RING_BYTES); + priv->desc_data[num].ptx_ring = (struct mwl_tx_desc *) + (mem + num * MAX_NUM_TX_RING_BYTES); - priv->desc_data[num].pphys_tx_ring = - (dma_addr_t)((u32)priv->desc_data[0].pphys_tx_ring + num * MAX_NUM_TX_RING_BYTES); + priv->desc_data[num].pphys_tx_ring = (dma_addr_t) + ((u32)priv->desc_data[0].pphys_tx_ring + + num * MAX_NUM_TX_RING_BYTES); - memset(priv->desc_data[num].ptx_ring, 0x00, MAX_NUM_TX_RING_BYTES); + memset(priv->desc_data[num].ptx_ring, 0x00, + MAX_NUM_TX_RING_BYTES); WLDBG_INFO(DBG_LEVEL_3, "TX ring vaddr: 0x%x paddr: 0x%x", - priv->desc_data[num].ptx_ring, priv->desc_data[num].pphys_tx_ring); + priv->desc_data[num].ptx_ring, + priv->desc_data[num].pphys_tx_ring); } WLDBG_EXIT(DBG_LEVEL_3); @@ -507,6 +528,7 @@ static int mwl_tx_ring_alloc(struct mwl_priv *priv) static int mwl_tx_ring_init(struct mwl_priv *priv) { int curr_desc; + struct mwl_desc_data *desc; int num; WLDBG_ENTER(DBG_LEVEL_3); @@ -517,30 +539,40 @@ static int mwl_tx_ring_init(struct mwl_priv *priv) skb_queue_head_init(&priv->txq[num]); priv->fw_desc_cnt[num] = 0; - if (priv->desc_data[num].ptx_ring != NULL) { - WLDBG_INFO(DBG_LEVEL_3, "initializing %i descriptors", SYSADPT_MAX_NUM_TX_DESC); + desc = &priv->desc_data[num]; + + if (desc->ptx_ring != NULL) { + WLDBG_INFO(DBG_LEVEL_3, "initializing %i descriptors", + SYSADPT_MAX_NUM_TX_DESC); - for (curr_desc = 0; curr_desc < SYSADPT_MAX_NUM_TX_DESC; curr_desc++) { - CURR_TXD(num).status = ENDIAN_SWAP32(EAGLE_TXD_STATUS_IDLE); + for (curr_desc = 0; curr_desc < SYSADPT_MAX_NUM_TX_DESC; + curr_desc++) { + CURR_TXD(num).status = + ENDIAN_SWAP32(EAGLE_TXD_STATUS_IDLE); CURR_TXD(num).pnext = &NEXT_TXD(num); CURR_TXD(num).pphys_next = - ENDIAN_SWAP32((u32)priv->desc_data[num].pphys_tx_ring + - ((curr_desc + 1) * sizeof(struct mwl_tx_desc))); + ENDIAN_SWAP32((u32)desc->pphys_tx_ring + + ((curr_desc + 1) * + sizeof(struct mwl_tx_desc))); WLDBG_INFO(DBG_LEVEL_3, - "txdesc: %i status: 0x%x (%i) vnext: 0x%p pnext: 0x%x", - curr_desc, EAGLE_TXD_STATUS_IDLE, EAGLE_TXD_STATUS_IDLE, - CURR_TXD(num).pnext, ENDIAN_SWAP32(CURR_TXD(num).pphys_next)); + "txdesc: %i 0x%x (%i) 0x%p 0x%x", + curr_desc, EAGLE_TXD_STATUS_IDLE, + EAGLE_TXD_STATUS_IDLE, + CURR_TXD(num).pnext, + ENDIAN_SWAP32( + CURR_TXD(num).pphys_next)); } LAST_TXD(num).pnext = &FIRST_TXD(num); LAST_TXD(num).pphys_next = - ENDIAN_SWAP32((u32)priv->desc_data[num].pphys_tx_ring); - priv->desc_data[num].pstale_tx_desc = &FIRST_TXD(num); - priv->desc_data[num].pnext_tx_desc = &FIRST_TXD(num); + ENDIAN_SWAP32((u32)desc->pphys_tx_ring); + desc->pstale_tx_desc = &FIRST_TXD(num); + desc->pnext_tx_desc = &FIRST_TXD(num); WLDBG_INFO(DBG_LEVEL_3, - "last txdesc vnext: 0x%p pnext: 0x%x pstale 0x%x vfirst 0x%x", - LAST_TXD(num).pnext, ENDIAN_SWAP32(LAST_TXD(num).pphys_next), - priv->desc_data[num].pstale_tx_desc, priv->desc_data[num].pnext_tx_desc); + "last txdesc vnext: 0x%p 0x%x 0x%x 0x%x", + LAST_TXD(num).pnext, + ENDIAN_SWAP32(LAST_TXD(num).pphys_next), + desc->pstale_tx_desc, desc->pnext_tx_desc); } else { WLDBG_ERROR(DBG_LEVEL_3, "no valid TX mem"); WLDBG_EXIT_INFO(DBG_LEVEL_3, "no valid memory"); @@ -567,23 +599,29 @@ static void mwl_tx_ring_cleanup(struct mwl_priv *priv) skb_queue_purge(&priv->txq[num]); priv->fw_desc_cnt[num] = 0; if (priv->desc_data[num].ptx_ring != NULL) { - for (curr_desc = 0; curr_desc < SYSADPT_MAX_NUM_TX_DESC; curr_desc++) { - if (CURR_TXD(num).psk_buff != NULL) { - WLDBG_INFO(DBG_LEVEL_3, - "unmapped and free'd txdesc %i vaddr: 0x%p paddr: 0x%x", - curr_desc, CURR_TXD(num).psk_buff->data, - ENDIAN_SWAP32(CURR_TXD(num).pkt_ptr)); - pci_unmap_single(priv->pdev, - ENDIAN_SWAP32(CURR_TXD(num).pkt_ptr), - CURR_TXD(num).psk_buff->len, - PCI_DMA_TODEVICE); - dev_kfree_skb_any(CURR_TXD(num).psk_buff); - CURR_TXD(num).status = ENDIAN_SWAP32(EAGLE_TXD_STATUS_IDLE); - CURR_TXD(num).psk_buff = NULL; - CURR_TXD(num).pkt_ptr = 0; - CURR_TXD(num).pkt_len = 0; - cleaned_tx_desc++; - } + for (curr_desc = 0; curr_desc < SYSADPT_MAX_NUM_TX_DESC; + curr_desc++) { + if (CURR_TXD(num).psk_buff == NULL) + continue; + + WLDBG_INFO(DBG_LEVEL_3, + "unmapped and free'd %i 0x%p 0x%x", + curr_desc, + CURR_TXD(num).psk_buff->data, + ENDIAN_SWAP32( + CURR_TXD(num).pkt_ptr)); + pci_unmap_single(priv->pdev, + ENDIAN_SWAP32( + CURR_TXD(num).pkt_ptr), + CURR_TXD(num).psk_buff->len, + PCI_DMA_TODEVICE); + dev_kfree_skb_any(CURR_TXD(num).psk_buff); + CURR_TXD(num).status = + ENDIAN_SWAP32(EAGLE_TXD_STATUS_IDLE); + CURR_TXD(num).psk_buff = NULL; + CURR_TXD(num).pkt_ptr = 0; + CURR_TXD(num).pkt_len = 0; + cleaned_tx_desc++; } } } @@ -617,7 +655,9 @@ static void mwl_tx_ring_free(struct mwl_priv *priv) } static inline void mwl_tx_add_dma_header(struct mwl_priv *priv, - struct sk_buff *skb, int head_pad, int tail_pad) + struct sk_buff *skb, + int head_pad, + int tail_pad) { struct ieee80211_hdr *wh; int hdrlen; @@ -725,23 +765,20 @@ static inline int mwl_tx_tid_queue_mapping(u8 tid) case 0: case 3: return IEEE80211_AC_BE; - break; case 1: case 2: return IEEE80211_AC_BK; - break; case 4: case 5: return IEEE80211_AC_VI; - break; case 6: case 7: return IEEE80211_AC_VO; - break; default: - return -1; break; } + + return -1; } static inline void mwl_tx_count_packet(struct ieee80211_sta *sta, u8 tid) @@ -776,6 +813,7 @@ static inline void mwl_tx_skbs(struct ieee80211_hw *hw) struct mwl_priv *priv; unsigned long flags; int num = SYSADPT_NUM_OF_DESC_DATA; + struct mwl_desc_data *desc; struct sk_buff *tx_skb; struct ieee80211_tx_info *tx_info; struct mwl_tx_ctrl *tx_ctrl; @@ -790,21 +828,29 @@ static inline void mwl_tx_skbs(struct ieee80211_hw *hw) while (num--) { while (skb_queue_len(&priv->txq[num]) > 0) { - if (priv->desc_data[num].pnext_tx_desc == NULL) + desc = &priv->desc_data[num]; + + if (desc->pnext_tx_desc == NULL) break; - /* Only queue to tx desc when Status is 0 (not when 0x1 or 0x80000000). If we queue even when Status==0x1 - * (DMA'd to fw but txdone haven't change Status to 0), mismatch of fwDescCnt with actual number of desc with Status==0 - * could happen. E.g fwDescCnt 256 instead of 255 when there is one desc with Status==0. This can cause Tx to stall - * when fwDescCnt==256 and pStaleTxDesc->Status==0. + /* Only queue to tx desc when Status is 0 (not when 0x1 + * or 0x80000000). If we queue even when Status==0x1 + * (DMA'd to fw but txdone haven't change Status to 0), + * mismatch of fwDescCnt with actual number of desc + * with Status==0 could happen. E.g fwDescCnt 256 + * instead of 255 when there is one desc with Status==0. + * This can cause Tx to stall when fwDescCnt==256 and + * pStaleTxDesc->Status==0. */ - if (priv->desc_data[num].pnext_tx_desc->status != EAGLE_TXD_STATUS_IDLE) { + if (desc->pnext_tx_desc->status != + EAGLE_TXD_STATUS_IDLE) { /* Interrupt F/W anyway */ - if (priv->desc_data[num].pnext_tx_desc->status & ENDIAN_SWAP32(EAGLE_TXD_STATUS_FW_OWNED)) + if (desc->pnext_tx_desc->status & + ENDIAN_SWAP32(EAGLE_TXD_STATUS_FW_OWNED)) writel(MACREG_H2ARIC_BIT_PPA_READY, - priv->iobase1 + MACREG_REG_H2A_INTERRUPT_EVENTS); - + priv->iobase1 + + MACREG_REG_H2A_INTERRUPT_EVENTS); break; } @@ -815,22 +861,29 @@ static inline void mwl_tx_skbs(struct ieee80211_hw *hw) tx_info = IEEE80211_SKB_CB(tx_skb); tx_ctrl = (struct mwl_tx_ctrl *)&tx_info->status; - priv->desc_data[num].pnext_tx_desc->tx_priority = tx_ctrl->tx_priority; - priv->desc_data[num].pnext_tx_desc->qos_ctrl = tx_ctrl->qos_ctrl; - priv->desc_data[num].pnext_tx_desc->psk_buff = tx_skb; - priv->desc_data[num].pnext_tx_desc->pkt_len = ENDIAN_SWAP16(tx_skb->len); - priv->desc_data[num].pnext_tx_desc->packet_info = 0; - priv->desc_data[num].pnext_tx_desc->data_rate = 0; - priv->desc_data[num].pnext_tx_desc->sta_info = tx_ctrl->sta_info; - priv->desc_data[num].pnext_tx_desc->type = tx_ctrl->type; - priv->desc_data[num].pnext_tx_desc->xmit_control = tx_ctrl->xmit_control; - priv->desc_data[num].pnext_tx_desc->sap_pkt_info = 0; - priv->desc_data[num].pnext_tx_desc->pkt_ptr = - ENDIAN_SWAP32(pci_map_single(priv->pdev, tx_skb->data, - tx_skb->len, PCI_DMA_TODEVICE)); - priv->desc_data[num].pnext_tx_desc->status = ENDIAN_SWAP32(EAGLE_TXD_STATUS_FW_OWNED); - priv->desc_data[num].pnext_tx_desc = priv->desc_data[num].pnext_tx_desc->pnext; - /* make sure all the memory transactions done by cpu were completed */ + desc->pnext_tx_desc->tx_priority = tx_ctrl->tx_priority; + desc->pnext_tx_desc->qos_ctrl = tx_ctrl->qos_ctrl; + desc->pnext_tx_desc->psk_buff = tx_skb; + desc->pnext_tx_desc->pkt_len = + ENDIAN_SWAP16(tx_skb->len); + desc->pnext_tx_desc->packet_info = 0; + desc->pnext_tx_desc->data_rate = 0; + desc->pnext_tx_desc->sta_info = tx_ctrl->sta_info; + desc->pnext_tx_desc->type = tx_ctrl->type; + desc->pnext_tx_desc->xmit_control = + tx_ctrl->xmit_control; + desc->pnext_tx_desc->sap_pkt_info = 0; + desc->pnext_tx_desc->pkt_ptr = + ENDIAN_SWAP32(pci_map_single(priv->pdev, + tx_skb->data, + tx_skb->len, + PCI_DMA_TODEVICE)); + desc->pnext_tx_desc->status = + ENDIAN_SWAP32(EAGLE_TXD_STATUS_FW_OWNED); + desc->pnext_tx_desc = desc->pnext_tx_desc->pnext; + /* make sure all the memory transactions done by cpu + * were completed + */ wmb(); /*Data Memory Barrier*/ writel(MACREG_H2ARIC_BIT_PPA_READY, priv->iobase1 + MACREG_REG_H2A_INTERRUPT_EVENTS); -- cgit v1.2.3