Commit mwlwifi driver 10.3.0.14.

Rollback the code to previous one which uses queue empty interrupt to flush AMSDU packets.

Signed-off-by: David Lin <dlin@marvell.com>

7 files changed, 146 insertions, 139 deletions

diff --git a/debugfs.c b/debugfs.c
index 2f6bae3..24f373c 100644
--- a/debugfs.c
+++ b/debugfs.c
@@ -283,14 +283,6 @@ static int mwl_debugfs_reg_access(struct mwl_priv *priv, bool write)
 	set = write ? WL_SET : WL_GET;
 
 	switch (priv->reg_type) {
-	case MWL_ACCESS_MAC:
-		if (set == WL_GET)
-			priv->reg_value =
-				le32_to_cpu(MAC_REG_ADDR_PCI(priv->reg_offset));
-		else
-			writel(cpu_to_le32(priv->reg_value),
-			       MAC_REG_ADDR_PCI(priv->reg_offset));
-		break;
 	case MWL_ACCESS_RF:
 		ret = mwl_fwcmd_reg_rf(hw, set, priv->reg_offset,
 				       &priv->reg_value);
diff --git a/dev.h b/dev.h
index 3f606fc..3f9a863 100644
--- a/dev.h
+++ b/dev.h
@@ -27,7 +27,7 @@
 #include <net/mac80211.h>
 
 #define MWL_DRV_NAME     KBUILD_MODNAME
-#define MWL_DRV_VERSION	 "10.3.0.13"
+#define MWL_DRV_VERSION	 "10.3.0.14"
 
 /* Map to 0x80000000 (Bus control) on BAR0 */
 #define MACREG_REG_H2A_INTERRUPT_EVENTS      0x00000C18 /* (From host to ARM) */
@@ -76,6 +76,7 @@
 			     MACREG_A2HRIC_BIT_RADAR_DETECT | \
 			     MACREG_A2HRIC_BIT_CHAN_SWITCH | \
 			     MACREG_A2HRIC_BIT_TX_WATCHDOG | \
+			     MACREG_A2HRIC_BIT_QUE_EMPTY | \
 			     MACREG_A2HRIC_BA_WATCHDOG | \
 			     MACREG_A2HRIC_CONSEC_TXFAIL)
 
@@ -319,11 +320,12 @@ struct mwl_priv {
 
 	struct tasklet_struct tx_task;
 	struct tasklet_struct rx_task;
+	struct tasklet_struct qe_task;
 	int txq_limit;
 	bool is_tx_schedule;
 	int recv_limit;
 	bool is_rx_schedule;
-	struct timer_list period_timer;
+	bool is_qe_schedule;
 	s8 noise;                    /* Most recently reported noise in dBm */
 	struct ieee80211_supported_band band_24;
 	struct ieee80211_channel channels_24[BAND_24_CHANNEL_NUM];
diff --git a/fwcmd.c b/fwcmd.c
index f754036..f879e1b 100644
--- a/fwcmd.c
+++ b/fwcmd.c
@@ -516,6 +516,7 @@ static int mwl_fwcmd_set_ies(struct mwl_priv *priv, struct mwl_vif *mwl_vif)
 {
 	struct hostcmd_cmd_set_ies *pcmd;
 	struct beacon_info *beacon = &mwl_vif->beacon_info;
+	u16 ie_list_len_proprietary = 0;
 
 	if (!beacon->valid)
 		return -EINVAL;
@@ -546,23 +547,23 @@ static int mwl_fwcmd_set_ies(struct mwl_priv *priv, struct mwl_vif *mwl_vif)
 #ifdef CONFIG_MAC80211_MESH
 	memcpy(pcmd->ie_list_proprietary, beacon->ie_meshid_ptr,
 	       beacon->ie_meshid_len);
-	pcmd->ie_list_len_proprietary = cpu_to_le16(beacon->ie_meshid_len);
-	memcpy(pcmd->ie_list_proprietary + pcmd->ie_list_len_proprietary,
+	ie_list_len_proprietary = beacon->ie_meshid_len;
+	memcpy(pcmd->ie_list_proprietary + ie_list_len_proprietary,
 	       beacon->ie_meshcfg_ptr, beacon->ie_meshcfg_len);
-	pcmd->ie_list_len_proprietary += cpu_to_le16(beacon->ie_meshcfg_len);
-	memcpy(pcmd->ie_list_proprietary + pcmd->ie_list_len_proprietary,
+	ie_list_len_proprietary += beacon->ie_meshcfg_len;
+	memcpy(pcmd->ie_list_proprietary + ie_list_len_proprietary,
 	       beacon->ie_meshchsw_ptr, beacon->ie_meshchsw_len);
-	pcmd->ie_list_len_proprietary += cpu_to_le16(beacon->ie_meshchsw_len);
+	ie_list_len_proprietary += beacon->ie_meshchsw_len;
 #endif
 
 	if (priv->chip_type == MWL8897) {
-		memcpy(pcmd->ie_list_proprietary +
-		       pcmd->ie_list_len_proprietary,
+		memcpy(pcmd->ie_list_proprietary + ie_list_len_proprietary,
 		       beacon->ie_wmm_ptr, beacon->ie_wmm_len);
-		pcmd->ie_list_len_proprietary +=
-			cpu_to_le16(mwl_vif->beacon_info.ie_wmm_len);
+		ie_list_len_proprietary += mwl_vif->beacon_info.ie_wmm_len;
 	}
 
+	pcmd->ie_list_len_proprietary = cpu_to_le16(ie_list_len_proprietary);
+
 	if (mwl_fwcmd_exec_cmd(priv, HOSTCMD_CMD_SET_IES)) {
 		spin_unlock_bh(&priv->fwcmd_lock);
 		wiphy_err(priv->hw->wiphy, "failed execution\n");
diff --git a/isr.c b/isr.c
index e44f66c..20b6088 100644
--- a/isr.c
+++ b/isr.c
@@ -66,6 +66,18 @@ irqreturn_t mwl_isr(int irq, void *dev_id)
 			}
 		}
 
+		if (int_status & MACREG_A2HRIC_BIT_QUE_EMPTY) {
+			int_status &= ~MACREG_A2HRIC_BIT_QUE_EMPTY;
+
+			if (!priv->is_qe_schedule) {
+				status = readl(int_status_mask);
+				writel((status & ~MACREG_A2HRIC_BIT_QUE_EMPTY),
+				       int_status_mask);
+				tasklet_schedule(&priv->qe_task);
+				priv->is_qe_schedule = true;
+			}
+		}
+
 		if (int_status & MACREG_A2HRIC_BA_WATCHDOG) {
 			status = readl(int_status_mask);
 			writel((status & ~MACREG_A2HRIC_BA_WATCHDOG),
diff --git a/mac80211.c b/mac80211.c
index e8dca94..85e5168 100644
--- a/mac80211.c
+++ b/mac80211.c
@@ -77,9 +77,7 @@ static int mwl_mac80211_start(struct ieee80211_hw *hw)
 	/* Enable TX reclaim and RX tasklets. */
 	tasklet_enable(&priv->tx_task);
 	tasklet_enable(&priv->rx_task);
-
-	/* Enable periodical timer */
-	mod_timer(&priv->period_timer, jiffies);
+	tasklet_enable(&priv->qe_task);
 
 	/* Enable interrupts */
 	mwl_fwcmd_int_enable(hw);
@@ -113,6 +111,7 @@ fwcmd_fail:
 	mwl_fwcmd_int_disable(hw);
 	tasklet_disable(&priv->tx_task);
 	tasklet_disable(&priv->rx_task);
+	tasklet_disable(&priv->qe_task);
 
 	return rc;
 }
@@ -131,6 +130,7 @@ static void mwl_mac80211_stop(struct ieee80211_hw *hw)
 	/* Disable TX reclaim and RX tasklets. */
 	tasklet_disable(&priv->tx_task);
 	tasklet_disable(&priv->rx_task);
+	tasklet_disable(&priv->qe_task);
 
 	/* Return all skbs to mac80211 */
 	mwl_tx_done((unsigned long)hw);
diff --git a/main.c b/main.c
index 962e566..ffe3f31 100644
--- a/main.c
+++ b/main.c
@@ -149,6 +149,109 @@ static const struct ieee80211_iface_combination ap_if_comb = {
 	.num_different_channels = 1,
 };
 
+static int mwl_alloc_pci_resource(struct mwl_priv *priv)
+{
+	struct pci_dev *pdev = priv->pdev;
+	void __iomem *addr;
+
+	priv->next_bar_num = 1;	/* 32-bit */
+	if (pci_resource_flags(pdev, 0) & 0x04)
+		priv->next_bar_num = 2;	/* 64-bit */
+
+	addr = devm_ioremap_resource(&pdev->dev, &pdev->resource[0]);
+	if (IS_ERR(addr)) {
+		wiphy_err(priv->hw->wiphy,
+			  "%s: cannot reserve PCI memory region 0\n",
+			  MWL_DRV_NAME);
+		goto err;
+	}
+	priv->iobase0 = addr;
+	wiphy_debug(priv->hw->wiphy, "priv->iobase0 = %p\n", priv->iobase0);
+
+	addr = devm_ioremap_resource(&pdev->dev,
+				     &pdev->resource[priv->next_bar_num]);
+	if (IS_ERR(addr)) {
+		wiphy_err(priv->hw->wiphy,
+			  "%s: cannot reserve PCI memory region 1\n",
+			  MWL_DRV_NAME);
+		goto err;
+	}
+	priv->iobase1 = addr;
+	wiphy_debug(priv->hw->wiphy, "priv->iobase1 = %p\n", priv->iobase1);
+
+	priv->pcmd_buf =
+		(unsigned short *)dmam_alloc_coherent(&priv->pdev->dev,
+						      CMD_BUF_SIZE,
+						      &priv->pphys_cmd_buf,
+						      GFP_KERNEL);
+	if (!priv->pcmd_buf) {
+		wiphy_err(priv->hw->wiphy,
+			  "%s: cannot alloc memory for command buffer\n",
+			  MWL_DRV_NAME);
+		goto err;
+	}
+	wiphy_debug(priv->hw->wiphy,
+		    "priv->pcmd_buf = %p  priv->pphys_cmd_buf = %p\n",
+		    priv->pcmd_buf,
+		    (void *)priv->pphys_cmd_buf);
+	memset(priv->pcmd_buf, 0x00, CMD_BUF_SIZE);
+
+	return 0;
+
+err:
+	wiphy_err(priv->hw->wiphy, "pci alloc fail\n");
+
+	return -EIO;
+}
+
+static int mwl_init_firmware(struct mwl_priv *priv, const char *fw_name)
+{
+	struct pci_dev *pdev;
+	int rc = 0;
+
+	pdev = priv->pdev;
+
+#ifdef CONFIG_SUPPORT_MFG
+	if (priv->mfg_mode)
+		rc = mwl_mfg_request_firmware(priv, fw_name);
+	else
+#endif
+		rc = request_firmware((const struct firmware **)&priv->fw_ucode,
+				      fw_name, &priv->pdev->dev);
+
+	if (rc) {
+		wiphy_err(priv->hw->wiphy,
+			  "%s: cannot load firmware image <%s>\n",
+			  MWL_DRV_NAME, fw_name);
+		goto err_load_fw;
+	}
+
+	rc = mwl_fwdl_download_firmware(priv->hw);
+	if (rc) {
+		wiphy_err(priv->hw->wiphy,
+			  "%s: cannot download firmware image <%s>\n",
+			  MWL_DRV_NAME, fw_name);
+		goto err_download_fw;
+	}
+
+	return rc;
+
+err_download_fw:
+
+#ifdef CONFIG_SUPPORT_MFG
+	if (priv->mfg_mode)
+		mwl_mfg_release_firmware(priv);
+	else
+#endif
+		release_firmware(priv->fw_ucode);
+
+err_load_fw:
+
+	wiphy_err(priv->hw->wiphy, "firmware init fail\n");
+
+	return rc;
+}
+
 static void mwl_reg_notifier(struct wiphy *wiphy,
 			     struct regulatory_request *request)
 {
@@ -261,109 +364,6 @@ static void mwl_reg_notifier(struct wiphy *wiphy,
 #endif
 }
 
-static int mwl_alloc_pci_resource(struct mwl_priv *priv)
-{
-	struct pci_dev *pdev = priv->pdev;
-	void __iomem *addr;
-
-	priv->next_bar_num = 1;	/* 32-bit */
-	if (pci_resource_flags(pdev, 0) & 0x04)
-		priv->next_bar_num = 2;	/* 64-bit */
-
-	addr = devm_ioremap_resource(&pdev->dev, &pdev->resource[0]);
-	if (IS_ERR(addr)) {
-		wiphy_err(priv->hw->wiphy,
-			  "%s: cannot reserve PCI memory region 0\n",
-			  MWL_DRV_NAME);
-		goto err;
-	}
-	priv->iobase0 = addr;
-	wiphy_debug(priv->hw->wiphy, "priv->iobase0 = %p\n", priv->iobase0);
-
-	addr = devm_ioremap_resource(&pdev->dev,
-				     &pdev->resource[priv->next_bar_num]);
-	if (IS_ERR(addr)) {
-		wiphy_err(priv->hw->wiphy,
-			  "%s: cannot reserve PCI memory region 1\n",
-			  MWL_DRV_NAME);
-		goto err;
-	}
-	priv->iobase1 = addr;
-	wiphy_debug(priv->hw->wiphy, "priv->iobase1 = %p\n", priv->iobase1);
-
-	priv->pcmd_buf =
-		(unsigned short *)dmam_alloc_coherent(&priv->pdev->dev,
-						      CMD_BUF_SIZE,
-						      &priv->pphys_cmd_buf,
-						      GFP_KERNEL);
-	if (!priv->pcmd_buf) {
-		wiphy_err(priv->hw->wiphy,
-			  "%s: cannot alloc memory for command buffer\n",
-			  MWL_DRV_NAME);
-		goto err;
-	}
-	wiphy_debug(priv->hw->wiphy,
-		    "priv->pcmd_buf = %p  priv->pphys_cmd_buf = %p\n",
-		    priv->pcmd_buf,
-		    (void *)priv->pphys_cmd_buf);
-	memset(priv->pcmd_buf, 0x00, CMD_BUF_SIZE);
-
-	return 0;
-
-err:
-	wiphy_err(priv->hw->wiphy, "pci alloc fail\n");
-
-	return -EIO;
-}
-
-static int mwl_init_firmware(struct mwl_priv *priv, const char *fw_name)
-{
-	struct pci_dev *pdev;
-	int rc = 0;
-
-	pdev = priv->pdev;
-
-#ifdef CONFIG_SUPPORT_MFG
-	if (priv->mfg_mode)
-		rc = mwl_mfg_request_firmware(priv, fw_name);
-	else
-#endif
-		rc = request_firmware((const struct firmware **)&priv->fw_ucode,
-				      fw_name, &priv->pdev->dev);
-
-	if (rc) {
-		wiphy_err(priv->hw->wiphy,
-			  "%s: cannot load firmware image <%s>\n",
-			  MWL_DRV_NAME, fw_name);
-		goto err_load_fw;
-	}
-
-	rc = mwl_fwdl_download_firmware(priv->hw);
-	if (rc) {
-		wiphy_err(priv->hw->wiphy,
-			  "%s: cannot download firmware image <%s>\n",
-			  MWL_DRV_NAME, fw_name);
-		goto err_download_fw;
-	}
-
-	return rc;
-
-err_download_fw:
-
-#ifdef CONFIG_SUPPORT_MFG
-	if (priv->mfg_mode)
-		mwl_mfg_release_firmware(priv);
-	else
-#endif
-		release_firmware(priv->fw_ucode);
-
-err_load_fw:
-
-	wiphy_err(priv->hw->wiphy, "firmware init fail\n");
-
-	return rc;
-}
-
 static void mwl_process_of_dts(struct mwl_priv *priv)
 {
 #ifdef CONFIG_OF
@@ -399,16 +399,6 @@ static void mwl_process_of_dts(struct mwl_priv *priv)
 #endif
 }
 
-static void mwl_period_timer(unsigned long data)
-{
-	struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
-	struct mwl_priv *priv = hw->priv;
-
-	mwl_tx_flush_amsdu(data);
-
-	mod_timer(&priv->period_timer, jiffies + 1);
-}
-
 static void mwl_set_ht_caps(struct mwl_priv *priv,
 			    struct ieee80211_supported_band *band)
 {
@@ -569,12 +559,14 @@ static int mwl_wl_init(struct mwl_priv *priv)
 	tasklet_disable(&priv->tx_task);
 	tasklet_init(&priv->rx_task, (void *)mwl_rx_recv, (unsigned long)hw);
 	tasklet_disable(&priv->rx_task);
+	tasklet_init(&priv->qe_task,
+		     (void *)mwl_tx_flush_amsdu, (unsigned long)hw);
+	tasklet_disable(&priv->qe_task);
 	priv->txq_limit = SYSADPT_TX_QUEUE_LIMIT;
 	priv->is_tx_schedule = false;
 	priv->recv_limit = SYSADPT_RECEIVE_LIMIT;
 	priv->is_rx_schedule = false;
-
-	setup_timer(&priv->period_timer, mwl_period_timer, (unsigned long)hw);
+	priv->is_qe_schedule = false;
 
 	spin_lock_init(&priv->tx_desc_lock);
 	spin_lock_init(&priv->rx_desc_lock);
@@ -693,7 +685,7 @@ static void mwl_wl_deinit(struct mwl_priv *priv)
 	ieee80211_unregister_hw(hw);
 	mwl_rx_deinit(hw);
 	mwl_tx_deinit(hw);
-	del_timer_sync(&priv->period_timer);
+	tasklet_kill(&priv->qe_task);
 	tasklet_kill(&priv->rx_task);
 	tasklet_kill(&priv->tx_task);
 	cancel_work_sync(&priv->watchdog_ba_handle);
@@ -766,7 +758,7 @@ static int mwl_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	if (mfg_mode) {
 		mwl_mfg_handler_init(priv);
 		fw_name = mwl_chip_tbl[priv->chip_type].mfg_fw_image;
-	}		
+	}
 #endif
 
 	rc = mwl_init_firmware(priv, fw_name);
diff --git a/tx.c b/tx.c
index 0a98ef8..85a7c7c 100644
--- a/tx.c
+++ b/tx.c
@@ -1180,6 +1180,7 @@ void mwl_tx_flush_amsdu(unsigned long data)
 {
 	struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 	struct mwl_priv *priv = hw->priv;
+	u32 status_mask;
 	struct mwl_sta *sta_info;
 	int i;
 	struct mwl_amsdu_frag *amsdu_frag;
@@ -1206,6 +1207,13 @@ void mwl_tx_flush_amsdu(unsigned long data)
 		spin_unlock(&priv->tx_desc_lock);
 	}
 	spin_unlock(&priv->sta_lock);
+
+	status_mask = readl(priv->iobase1 +
+			    MACREG_REG_A2H_INTERRUPT_STATUS_MASK);
+	writel(status_mask | MACREG_A2HRIC_BIT_QUE_EMPTY,
+	       priv->iobase1 + MACREG_REG_A2H_INTERRUPT_STATUS_MASK);
+
+	priv->is_qe_schedule = false;
 }
 
 void mwl_tx_del_sta_amsdu_pkts(struct ieee80211_sta *sta)