From 651ef18db973f8543faf8a7450484502f916a936 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 23 Apr 2012 15:42:54 +0000 Subject: ARM: bcmring: move cfg_global header to mach/ Platforms should not have header files outside of include/mach, and bcmring is the only one that has one just under include/, so move that away. Signed-off-by: Arnd Bergmann --- arch/arm/mach-bcmring/arch.c | 2 +- arch/arm/mach-bcmring/core.c | 2 +- arch/arm/mach-bcmring/include/cfg_global.h | 13 ------ arch/arm/mach-bcmring/include/cfg_global_defines.h | 40 ----------------- arch/arm/mach-bcmring/include/mach/cfg_global.h | 51 ++++++++++++++++++++++ .../arm/mach-bcmring/include/mach/csp/cap_inline.h | 2 +- arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h | 2 +- arch/arm/mach-bcmring/include/mach/csp/mm_addr.h | 2 +- arch/arm/mach-bcmring/include/mach/csp/mm_io.h | 2 +- arch/arm/mach-bcmring/include/mach/hardware.h | 2 +- drivers/mtd/nand/nand_bcm_umi.h | 2 +- 11 files changed, 59 insertions(+), 61 deletions(-) delete mode 100644 arch/arm/mach-bcmring/include/cfg_global.h delete mode 100644 arch/arm/mach-bcmring/include/cfg_global_defines.h create mode 100644 arch/arm/mach-bcmring/include/mach/cfg_global.h diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c index 45c97b1ee9b..7799e910e27 100644 --- a/arch/arm/mach-bcmring/arch.c +++ b/arch/arm/mach-bcmring/arch.c @@ -38,7 +38,7 @@ #include #include -#include +#include #include "core.h" diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index adbfb199458..0d0c277affc 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c @@ -43,7 +43,7 @@ #include #include -#include +#include #include "clock.h" diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h deleted file mode 100644 index f01da877148..00000000000 --- a/arch/arm/mach-bcmring/include/cfg_global.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _CFG_GLOBAL_H_ -#define _CFG_GLOBAL_H_ - -#include - -#define CFG_GLOBAL_CHIP BCM11107 -#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING -#define CFG_GLOBAL_CHIP_REV 0xB0 -#define CFG_GLOBAL_RAM_SIZE 0x10000000 -#define CFG_GLOBAL_RAM_BASE 0x00000000 -#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 - -#endif /* _CFG_GLOBAL_H_ */ diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/cfg_global_defines.h deleted file mode 100644 index b5beb0b3073..00000000000 --- a/arch/arm/mach-bcmring/include/cfg_global_defines.h +++ /dev/null @@ -1,40 +0,0 @@ -/***************************************************************************** -* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CFG_GLOBAL_DEFINES_H -#define CFG_GLOBAL_DEFINES_H - -/* CHIP */ -#define BCM1103 1 - -#define BCM1191 4 -#define BCM2153 5 -#define BCM2820 6 - -#define BCM2826 8 -#define FPGA11107 9 -#define BCM11107 10 -#define BCM11109 11 -#define BCM11170 12 -#define BCM11110 13 -#define BCM11211 14 - -/* CFG_GLOBAL_CHIP_FAMILY types */ -#define CFG_GLOBAL_CHIP_FAMILY_NONE 0 -#define CFG_GLOBAL_CHIP_FAMILY_BCM116X 2 -#define CFG_GLOBAL_CHIP_FAMILY_BCMRING 4 -#define CFG_GLOBAL_CHIP_FAMILY_BCM1103 8 - -#define IMAGE_HEADER_SIZE_CHECKSUM 4 -#endif diff --git a/arch/arm/mach-bcmring/include/mach/cfg_global.h b/arch/arm/mach-bcmring/include/mach/cfg_global.h new file mode 100644 index 00000000000..449133eacdf --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/cfg_global.h @@ -0,0 +1,51 @@ +/***************************************************************************** +* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +#ifndef CFG_GLOBAL_DEFINES_H +#define CFG_GLOBAL_DEFINES_H + +/* CHIP */ +#define BCM1103 1 + +#define BCM1191 4 +#define BCM2153 5 +#define BCM2820 6 + +#define BCM2826 8 +#define FPGA11107 9 +#define BCM11107 10 +#define BCM11109 11 +#define BCM11170 12 +#define BCM11110 13 +#define BCM11211 14 + +/* CFG_GLOBAL_CHIP_FAMILY types */ +#define CFG_GLOBAL_CHIP_FAMILY_NONE 0 +#define CFG_GLOBAL_CHIP_FAMILY_BCM116X 2 +#define CFG_GLOBAL_CHIP_FAMILY_BCMRING 4 +#define CFG_GLOBAL_CHIP_FAMILY_BCM1103 8 + +#define IMAGE_HEADER_SIZE_CHECKSUM 4 +#endif +#ifndef _CFG_GLOBAL_H_ +#define _CFG_GLOBAL_H_ + +#define CFG_GLOBAL_CHIP BCM11107 +#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING +#define CFG_GLOBAL_CHIP_REV 0xB0 +#define CFG_GLOBAL_RAM_SIZE 0x10000000 +#define CFG_GLOBAL_RAM_BASE 0x00000000 +#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 + +#endif /* _CFG_GLOBAL_H_ */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h index 933ce68ed90..0a89e0c6341 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h @@ -17,7 +17,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include -#include +#include /* ---- Public Constants and Types --------------------------------------- */ #define CAP_CONFIG0_VPM_DIS 0x00000001 diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h index cfa91bed9d3..27f59dd2779 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h @@ -18,7 +18,7 @@ /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include #if defined(__KERNEL__) diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h index ad58cf87337..d571962f290 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h +++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h @@ -29,7 +29,7 @@ /* ---- Include Files ---------------------------------------------------- */ #if !defined(CSP_SIMULATION) -#include +#include #endif /* ---- Public Constants and Types --------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h index de92ec6a01a..dbc98ddaeb6 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h +++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h @@ -30,7 +30,7 @@ #include #if !defined(CSP_SIMULATION) -#include +#include #endif /* ---- Public Constants and Types --------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h index 6ae20a649a9..a0c92b4b8c6 100644 --- a/arch/arm/mach-bcmring/include/mach/hardware.h +++ b/arch/arm/mach-bcmring/include/mach/hardware.h @@ -22,7 +22,7 @@ #define __ASM_ARCH_HARDWARE_H #include -#include +#include #include /* Hardware addresses of major areas. diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h index 198b304d6f7..a158d5dd9a0 100644 --- a/drivers/mtd/nand/nand_bcm_umi.h +++ b/drivers/mtd/nand/nand_bcm_umi.h @@ -17,7 +17,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include #include -#include +#include /* ---- Constants and Types ---------------------------------------------- */ #if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING) -- cgit v1.2.3 From 8a3fb8607a48ed74db3aaa87d8af7febcaa5d814 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 24 Apr 2012 15:51:47 +0000 Subject: ARM: bcmring: remove include/csp/ subdir The csp/*.h headers get into the way of multiplatform kernels and are generally not needed anyway. This removes the ones that are completely free of content and moves the other ones to mach/csp/, which already holds a bunch of these. Signed-off-by: Arnd Bergmann --- arch/arm/mach-bcmring/core.c | 1 - arch/arm/mach-bcmring/csp/chipc/chipcHw.c | 10 +- arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c | 10 +- arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c | 8 +- arch/arm/mach-bcmring/csp/dmac/dmacHw.c | 6 +- arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c | 4 +- arch/arm/mach-bcmring/csp/tmr/tmrHw.c | 6 +- arch/arm/mach-bcmring/include/csp/cache.h | 35 -- arch/arm/mach-bcmring/include/csp/delay.h | 36 -- arch/arm/mach-bcmring/include/csp/dmacHw.h | 596 --------------------- arch/arm/mach-bcmring/include/csp/errno.h | 32 -- arch/arm/mach-bcmring/include/csp/intcHw.h | 40 -- arch/arm/mach-bcmring/include/csp/module.h | 32 -- arch/arm/mach-bcmring/include/csp/reg.h | 114 ---- arch/arm/mach-bcmring/include/csp/secHw.h | 65 --- arch/arm/mach-bcmring/include/csp/stdint.h | 30 -- arch/arm/mach-bcmring/include/csp/string.h | 34 -- arch/arm/mach-bcmring/include/csp/tmrHw.h | 263 --------- .../mach-bcmring/include/mach/csp/chipcHw_def.h | 6 +- .../mach-bcmring/include/mach/csp/chipcHw_inline.h | 4 +- .../mach-bcmring/include/mach/csp/chipcHw_reg.h | 2 +- arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h | 4 +- arch/arm/mach-bcmring/include/mach/csp/dmacHw.h | 596 +++++++++++++++++++++ .../mach-bcmring/include/mach/csp/dmacHw_priv.h | 2 +- .../arm/mach-bcmring/include/mach/csp/dmacHw_reg.h | 2 +- .../arm/mach-bcmring/include/mach/csp/intcHw_reg.h | 4 +- arch/arm/mach-bcmring/include/mach/csp/reg.h | 114 ++++ arch/arm/mach-bcmring/include/mach/csp/tmrHw.h | 263 +++++++++ arch/arm/mach-bcmring/include/mach/dma.h | 2 +- arch/arm/mach-bcmring/include/mach/reg_nand.h | 2 +- arch/arm/mach-bcmring/include/mach/reg_umi.h | 2 +- arch/arm/mach-bcmring/timer.c | 2 +- 32 files changed, 1011 insertions(+), 1316 deletions(-) delete mode 100644 arch/arm/mach-bcmring/include/csp/cache.h delete mode 100644 arch/arm/mach-bcmring/include/csp/delay.h delete mode 100644 arch/arm/mach-bcmring/include/csp/dmacHw.h delete mode 100644 arch/arm/mach-bcmring/include/csp/errno.h delete mode 100644 arch/arm/mach-bcmring/include/csp/intcHw.h delete mode 100644 arch/arm/mach-bcmring/include/csp/module.h delete mode 100644 arch/arm/mach-bcmring/include/csp/reg.h delete mode 100644 arch/arm/mach-bcmring/include/csp/secHw.h delete mode 100644 arch/arm/mach-bcmring/include/csp/stdint.h delete mode 100644 arch/arm/mach-bcmring/include/csp/string.h delete mode 100644 arch/arm/mach-bcmring/include/csp/tmrHw.h create mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw.h create mode 100644 arch/arm/mach-bcmring/include/mach/csp/reg.h create mode 100644 arch/arm/mach-bcmring/include/mach/csp/tmrHw.h diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index 0d0c277affc..4b50228a677 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c @@ -47,7 +47,6 @@ #include "clock.h" -#include #include #include #include diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c index 96273ff3495..5ac7e250972 100644 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c index 367df75d4bb..a711d9bdf31 100644 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ /* diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c index 2671d8896bb..74d2b023dce 100644 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c @@ -13,11 +13,11 @@ *****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ /* ---- Private Variables ------------------------------------------------- */ @@ -60,7 +60,7 @@ void chipcHw_reset(uint32_t mask) i++; } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ - CSP_CACHE_FLUSH_ALL; + flush_cache_all(); /* run the function from ARAM */ runFunc(); diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c index 6b9be2e98e5..570ab0ab923 100644 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c @@ -25,11 +25,11 @@ /****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c index a1f328357aa..ea0bd642b36 100644 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include -#include +#include #include #include diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c index 16225e43f3c..dc4137ff75c 100644 --- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c +++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include -#include +#include #include #define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0 diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h deleted file mode 100644 index caa20e59db9..00000000000 --- a/arch/arm/mach-bcmring/include/csp/cache.h +++ /dev/null @@ -1,35 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_CACHE_H -#define CSP_CACHE_H - -/* ---- Include Files ---------------------------------------------------- */ - -#include - -/* ---- Public Constants and Types --------------------------------------- */ - -#if defined(__KERNEL__) && !defined(STANDALONE) -#include - -#define CSP_CACHE_FLUSH_ALL flush_cache_all() - -#else - -#define CSP_CACHE_FLUSH_ALL - -#endif - -#endif /* CSP_CACHE_H */ diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h deleted file mode 100644 index 8b3d8036729..00000000000 --- a/arch/arm/mach-bcmring/include/csp/delay.h +++ /dev/null @@ -1,36 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -#ifndef CSP_DELAY_H -#define CSP_DELAY_H - -/* ---- Include Files ---------------------------------------------------- */ - -/* Some CSP routines require use of the following delay routines. Use the OS */ -/* version if available, otherwise use a CSP specific definition. */ -/* void udelay(unsigned long usecs); */ -/* void mdelay(unsigned long msecs); */ - -#if defined(__KERNEL__) && !defined(STANDALONE) - #include -#else - #include -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_DELAY_H */ diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h deleted file mode 100644 index e6a1dc484ca..00000000000 --- a/arch/arm/mach-bcmring/include/csp/dmacHw.h +++ /dev/null @@ -1,596 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file dmacHw.h -* -* @brief API definitions for low level DMA controller driver -* -*/ -/****************************************************************************/ -#ifndef _DMACHW_H -#define _DMACHW_H - -#include - -#include -#include - -/* Define DMA Channel ID using DMA controller number (m) and channel number (c). - - System specific channel ID should be defined as follows - - For example: - - #include - ... - #define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5) - #define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0) - #define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1) - #define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3) - #define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4) - ... - #define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4) - #define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5) - #define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6) - ... -*/ -#define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c) - -typedef enum { - dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */ - dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */ - dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */ - dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */ - dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */ - dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */ - dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */ - dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */ -} dmacHw_CHANNEL_PRIORITY_e; - -/* Source destination master interface */ -typedef enum { - dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */ - dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */ - dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */ - dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */ -} dmacHw_MASTER_INTERFACE_e; - -typedef enum { - dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */ - dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */ - dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */ - dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */ - dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */ - dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */ - dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */ - dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */ -} dmacHw_TRANSACTION_WIDTH_e; - -typedef enum { - dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */ - dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */ - dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ -} dmacHw_BURST_WIDTH_e; - -typedef enum { - dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */ - dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */ - dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */ - dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */ -} dmacHw_TRANSFER_TYPE_e; - -typedef enum { - dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */ - dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */ - dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */ -} dmacHw_TRANSFER_MODE_e; - -typedef enum { - dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */ - dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */ - dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */ - dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */ - dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */ - dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */ -} dmacHw_ADDRESS_UPDATE_MODE_e; - -typedef enum { - dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */ - dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */ -} dmacHw_FLOW_CONTROL_e; - -typedef enum { - dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */ - dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */ - dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */ -} dmacHw_TRANSFER_STATUS_e; - -typedef enum { - dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */ - dmacHw_INTERRUPT_ENABLE /* Interrupt enable */ -} dmacHw_INTERRUPT_e; - -typedef enum { - dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */ - dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */ - dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */ - dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */ -} dmacHw_INTERRUPT_STATUS_e; - -typedef enum { - dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */ - dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */ - dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */ - dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */ - dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */ -} dmacHw_CONTROLLER_ATTRIB_e; - -typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */ -typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using - "dmacHw_MAKE_CHANNEL_ID" macro - */ -/* DMA channel configuration parameters */ -typedef struct { - uint32_t srcPeripheralPort; /* Source peripheral port */ - uint32_t dstPeripheralPort; /* Destination peripheral port */ - uint32_t srcStatusRegisterAddress; /* Source status register address */ - uint32_t dstStatusRegisterAddress; /* Destination status register address of type */ - - uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */ - uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */ - uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */ - uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */ - uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor. - 0 = Maximum possible. - */ - - dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */ - dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */ - dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */ - dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */ - dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */ - dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */ - dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */ - dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */ - dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */ - dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */ - dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */ - dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */ - dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */ - dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */ - dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */ -} dmacHw_CONFIG_t; - -/****************************************************************************/ -/** -* @brief Initializes DMA -* -* This function initializes DMA CSP driver -* -* @note -* Must be called before using any DMA channel -*/ -/****************************************************************************/ -void dmacHw_initDma(void); - -/****************************************************************************/ -/** -* @brief Exit function for DMA -* -* This function isolates DMA from the system -* -*/ -/****************************************************************************/ -void dmacHw_exitDma(void); - -/****************************************************************************/ -/** -* @brief Gets a handle to a DMA channel -* -* This function returns a handle, representing a control block of a particular DMA channel -* -* @return -1 - On Failure -* handle - On Success, representing a channel control block -* -* @note -* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro -*/ -/****************************************************************************/ -dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */ - ); - -/****************************************************************************/ -/** -* @brief Initializes a DMA channel for use -* -* This function initializes and resets a DMA channel for use -* -* @return -1 - On Failure -* 0 - On Success -* -* @note -* None -*/ -/****************************************************************************/ -int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Estimates number of descriptor needed to perform certain DMA transfer -* -* -* @return On failure : -1 -* On success : Number of descriptor count -* -* -*/ -/****************************************************************************/ -int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ - void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ - size_t dataLen /* [ IN ] Data length in bytes */ - ); - -/****************************************************************************/ -/** -* @brief Initializes descriptor ring -* -* This function will initializes the descriptor ring of a DMA channel -* -* -* @return -1 - On failure -* 0 - On success -* @note -* - "len" parameter should be obtained from "dmacHw_descriptorLen" -* - Descriptor buffer MUST be 32 bit aligned and uncached as it -* is accessed by ARM and DMA -*/ -/****************************************************************************/ -int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */ - uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */ - uint32_t len, /* [ IN ] Size of the pBuf */ - uint32_t num /* [ IN ] Number of descriptor in the ring */ - ); - -/****************************************************************************/ -/** -* @brief Finds amount of memory required to form a descriptor ring -* -* -* @return Number of bytes required to form a descriptor ring -* -* -* @note -* None -*/ -/****************************************************************************/ -uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */ - ); - -/****************************************************************************/ -/** -* @brief Configure DMA channel -* -* @return 0 : On success -* -1 : On failure -*/ -/****************************************************************************/ -int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */ - ); - -/****************************************************************************/ -/** -* @brief Set descriptors for known data length -* -* When DMA has to work as a flow controller, this function prepares the -* descriptor chain to transfer data -* -* from: -* - Memory to memory -* - Peripheral to memory -* - Memory to Peripheral -* - Peripheral to Peripheral -* -* @return -1 - On failure -* 0 - On success -* -*/ -/****************************************************************************/ -int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ - void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ - size_t dataLen /* [ IN ] Length in bytes */ - ); - -/****************************************************************************/ -/** -* @brief Indicates whether DMA transfer is in progress or completed -* -* @return DMA transfer status -* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing -* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed -* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error -* -*/ -/****************************************************************************/ -dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Set descriptor carrying control information -* -* This function will be used to send specific control information to the device -* using the DMA channel -* -* -* @return -1 - On failure -* 0 - On success -* -* @note -* None -*/ -/****************************************************************************/ -int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - uint32_t ctlAddress, /* [ IN ] Address of the device control register */ - uint32_t control /* [ IN ] Device control information */ - ); - -/****************************************************************************/ -/** -* @brief Read data DMA transferred to memory -* -* This function will read data that has been DMAed to memory while transferring from: -* - Memory to memory -* - Peripheral to memory -* -* @return 0 - No more data is available to read -* 1 - More data might be available to read -* -*/ -/****************************************************************************/ -int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - void **ppBbuf, /* [ OUT ] Data received */ - size_t *pLlen /* [ OUT ] Length of the data received */ - ); - -/****************************************************************************/ -/** -* @brief Prepares descriptor ring, when source peripheral working as a flow controller -* -* This function will form the descriptor ring by allocating buffers, when source peripheral -* has to work as a flow controller to transfer data from: -* - Peripheral to memory. -* -* @return -1 - On failure -* 0 - On success -* -* -* @note -* None -*/ -/****************************************************************************/ -int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - uint32_t srcAddr, /* [ IN ] Source peripheral address */ - void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */ - int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */ - int num /* [ IN ] Number of descriptor to set */ - ); - -/****************************************************************************/ -/** -* @brief Program channel register to initiate transfer -* -* @return void -* -* -* @note -* - Descriptor buffer MUST ALWAYS be flushed before calling this function -* - This function should also be called from ISR to program the channel with -* pending descriptors -*/ -/****************************************************************************/ -void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor /* [ IN ] Descriptor buffer */ - ); - -/****************************************************************************/ -/** -* @brief Resets descriptor control information -* -* @return void -*/ -/****************************************************************************/ -void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */ - ); - -/****************************************************************************/ -/** -* @brief Program channel register to stop transfer -* -* Ensures the channel is not doing any transfer after calling this function -* -* @return void -* -*/ -/****************************************************************************/ -void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Check the existence of pending descriptor -* -* This function confirmes if there is any pending descriptor in the chain -* to program the channel -* -* @return 1 : Channel need to be programmed with pending descriptor -* 0 : No more pending descriptor to programe the channel -* -* @note -* - This function should be called from ISR in case there are pending -* descriptor to program the channel. -* -* Example: -* -* dmac_isr () -* { -* ... -* if (dmacHw_descriptorPending (handle)) -* { -* dmacHw_initiateTransfer (handle); -* } -* } -* -*/ -/****************************************************************************/ -uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - void *pDescriptor /* [ IN ] Descriptor buffer */ - ); - -/****************************************************************************/ -/** -* @brief Deallocates source or destination memory, allocated -* -* This function can be called to deallocate data memory that was DMAed successfully -* -* @return -1 - On failure -* 0 - On success -* -* @note -* This function will be called ONLY, when source OR destination address is pointing -* to dynamic memory -*/ -/****************************************************************************/ -int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */ - ); - -/****************************************************************************/ -/** -* @brief Clears the interrupt -* -* This function clears the DMA channel specific interrupt -* -* @return N/A -* -* @note -* Must be called under the context of ISR -*/ -/****************************************************************************/ -void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Returns the cause of channel specific DMA interrupt -* -* This function returns the cause of interrupt -* -* @return Interrupt status, each bit representing a specific type of interrupt -* of type dmacHw_INTERRUPT_STATUS_e -* @note -* This function should be called under the context of ISR -*/ -/****************************************************************************/ -dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Indentifies a DMA channel causing interrupt -* -* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e -* -* @return NULL : No channel causing DMA interrupt -* ! NULL : Handle to a channel causing DMA interrupt -* @note -* dmacHw_clearInterrupt() must be called with a valid handle after calling this function -*/ -/****************************************************************************/ -dmacHw_HANDLE_t dmacHw_getInterruptSource(void); - -/****************************************************************************/ -/** -* @brief Sets channel specific user data -* -* This function associates user data to a specific DMA channel -* -*/ -/****************************************************************************/ -void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - void *userData /* [ IN ] User data */ - ); - -/****************************************************************************/ -/** -* @brief Gets channel specific user data -* -* This function returns user data specific to a DMA channel -* -* @return user data -*/ -/****************************************************************************/ -void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Displays channel specific registers and other control parameters -* -* -* @return void -* -* @note -* None -*/ -/****************************************************************************/ -void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ - ); - -/****************************************************************************/ -/** -* @brief Provides DMA controller attributes -* -* -* @return DMA controller attributes -* -* @note -* None -*/ -/****************************************************************************/ -uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */ - ); - -#endif /* _DMACHW_H */ diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h deleted file mode 100644 index 51357dd5b66..00000000000 --- a/arch/arm/mach-bcmring/include/csp/errno.h +++ /dev/null @@ -1,32 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_ERRNO_H -#define CSP_ERRNO_H - -/* ---- Include Files ---------------------------------------------------- */ - -#if defined(__KERNEL__) -#include -#elif defined(CSP_SIMULATION) -#include -#else -#include -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_ERRNO_H */ diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h deleted file mode 100644 index 1c639c8ee08..00000000000 --- a/arch/arm/mach-bcmring/include/csp/intcHw.h +++ /dev/null @@ -1,40 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -/****************************************************************************/ -/** -* @file intcHw.h -* -* @brief generic interrupt controller API -* -* @note -* None -*/ -/****************************************************************************/ - -#ifndef _INTCHW_H -#define _INTCHW_H - -/* ---- Include Files ---------------------------------------------------- */ -#include - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ -static inline void intcHw_irq_disable(void *basep, uint32_t mask); -static inline void intcHw_irq_enable(void *basep, uint32_t mask); - -#endif /* _INTCHW_H */ - diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h deleted file mode 100644 index c30d2a5975a..00000000000 --- a/arch/arm/mach-bcmring/include/csp/module.h +++ /dev/null @@ -1,32 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -#ifndef CSP_MODULE_H -#define CSP_MODULE_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ - #include -#else - #define EXPORT_SYMBOL(symbol) -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - - -#endif /* CSP_MODULE_H */ diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h deleted file mode 100644 index 56654d23c3d..00000000000 --- a/arch/arm/mach-bcmring/include/csp/reg.h +++ /dev/null @@ -1,114 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file reg.h -* -* @brief Generic register definitions used in CSP -*/ -/****************************************************************************/ - -#ifndef CSP_REG_H -#define CSP_REG_H - -/* ---- Include Files ---------------------------------------------------- */ - -#include - -/* ---- Public Constants and Types --------------------------------------- */ - -#define __REG32(x) (*((volatile uint32_t *)(x))) -#define __REG16(x) (*((volatile uint16_t *)(x))) -#define __REG8(x) (*((volatile uint8_t *) (x))) - -/* Macros used to define a sequence of reserved registers. The start / end */ -/* are byte offsets in the particular register definition, with the "end" */ -/* being the offset of the next un-reserved register. E.g. if offsets */ -/* 0x10 through to 0x1f are reserved, then this reserved area could be */ -/* specified as follows. */ -/* typedef struct */ -/* { */ -/* uint32_t reg1; offset 0x00 */ -/* uint32_t reg2; offset 0x04 */ -/* uint32_t reg3; offset 0x08 */ -/* uint32_t reg4; offset 0x0c */ -/* REG32_RSVD(0x10, 0x20); */ -/* uint32_t reg5; offset 0x20 */ -/* ... */ -/* } EXAMPLE_REG_t; */ -#define REG8_RSVD(start, end) uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)] -#define REG16_RSVD(start, end) uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)] -#define REG32_RSVD(start, end) uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)] - -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */ -/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the */ -/* flags variable to be declared locally. */ -/* e.g. */ -/* statement1; */ -/* { */ -/* REG_LOCAL_IRQ_SAVE; */ -/* */ -/* REG_LOCAL_IRQ_RESTORE; */ -/* } */ -/* statement2; */ -/* */ - -#if defined(__KERNEL__) && !defined(STANDALONE) -#include -#include - -#define REG_LOCAL_IRQ_SAVE HW_DECLARE_SPINLOCK(reg32) \ - unsigned long flags; HW_IRQ_SAVE(reg32, flags) - -#define REG_LOCAL_IRQ_RESTORE HW_IRQ_RESTORE(reg32, flags) - -#else - -#define REG_LOCAL_IRQ_SAVE -#define REG_LOCAL_IRQ_RESTORE - -#endif - -static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) -{ - REG_LOCAL_IRQ_SAVE; - *reg &= value; - REG_LOCAL_IRQ_RESTORE; -} - -static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) -{ - REG_LOCAL_IRQ_SAVE; - *reg |= value; - REG_LOCAL_IRQ_RESTORE; -} - -static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, - uint32_t value) -{ - REG_LOCAL_IRQ_SAVE; - *reg = (*reg & mask) | value; - REG_LOCAL_IRQ_RESTORE; -} - -static inline void reg32_write(volatile uint32_t *reg, uint32_t value) -{ - *reg = value; -} - -#endif /* CSP_REG_H */ diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h deleted file mode 100644 index b9d7e0732df..00000000000 --- a/arch/arm/mach-bcmring/include/csp/secHw.h +++ /dev/null @@ -1,65 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file secHw.h -* -* @brief Definitions for accessing low level security features -* -*/ -/****************************************************************************/ -#ifndef SECHW_H -#define SECHW_H - -typedef void (*secHw_FUNC_t) (void); - -typedef enum { - secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */ - secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */ -} secHw_MODE; - -/****************************************************************************/ -/** -* @brief Requesting to execute the function in secure mode -* -* This function requests the given function to run in secure mode -* -*/ -/****************************************************************************/ -void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */ - ); - -/****************************************************************************/ -/** -* @brief Sets the mode -* -* his function sets the processor mode (secure/non-secure) -* -*/ -/****************************************************************************/ -void secHw_SetMode(secHw_MODE /* Processor mode */ - ); - -/****************************************************************************/ -/** -* @brief Get the current mode -* -* This function retieves the processor mode (secure/non-secure) -* -*/ -/****************************************************************************/ -void secHw_GetMode(secHw_MODE *); - -#endif /* SECHW_H */ diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h deleted file mode 100644 index 3a8718bbf70..00000000000 --- a/arch/arm/mach-bcmring/include/csp/stdint.h +++ /dev/null @@ -1,30 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_STDINT_H -#define CSP_STDINT_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ -#include -#else -#include -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_STDINT_H */ diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h deleted file mode 100644 index ad9e4005f14..00000000000 --- a/arch/arm/mach-bcmring/include/csp/string.h +++ /dev/null @@ -1,34 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - - -#ifndef CSP_STRING_H -#define CSP_STRING_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ - #include -#else - #include -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - - -#endif /* CSP_STRING_H */ - diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/csp/tmrHw.h deleted file mode 100644 index 2cbb530db8e..00000000000 --- a/arch/arm/mach-bcmring/include/csp/tmrHw.h +++ /dev/null @@ -1,263 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file tmrHw.h -* -* @brief API definitions for low level Timer driver -* -*/ -/****************************************************************************/ -#ifndef _TMRHW_H -#define _TMRHW_H - -#include - -typedef uint32_t tmrHw_ID_t; /* Timer ID */ -typedef uint32_t tmrHw_COUNT_t; /* Timer count */ -typedef uint32_t tmrHw_INTERVAL_t; /* Timer interval */ -typedef uint32_t tmrHw_RATE_t; /* Timer event (count/interrupt) rate */ - -typedef enum { - tmrHw_INTERRUPT_STATUS_SET, /* Interrupted */ - tmrHw_INTERRUPT_STATUS_UNSET /* No Interrupt */ -} tmrHw_INTERRUPT_STATUS_e; - -typedef enum { - tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */ - tmrHw_CAPABILITY_RESOLUTION /* Timer resolution in bits */ -} tmrHw_CAPABILITY_e; - -/****************************************************************************/ -/** -* @brief Get timer capability -* -* This function returns various capabilities/attributes of a timer -* -* @return Numeric capability -* -*/ -/****************************************************************************/ -uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */ -); - -/****************************************************************************/ -/** -* @brief Configures a periodic timer in terms of timer interrupt rate -* -* This function initializes a periodic timer to generate specific number of -* timer interrupt per second -* -* @return On success: Effective timer frequency -* On failure: 0 -* -*/ -/****************************************************************************/ -tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */ -); - -/****************************************************************************/ -/** -* @brief Configures a periodic timer to generate timer interrupt after -* certain time interval -* -* This function initializes a periodic timer to generate timer interrupt -* after every time interval in millisecond -* -* @return On success: Effective interval set in mili-second -* On failure: 0 -* -*/ -/****************************************************************************/ -tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */ -); - -/****************************************************************************/ -/** -* @brief Configures a periodic timer to generate timer interrupt just once -* after certain time interval -* -* This function initializes a periodic timer to generate a single ticks after -* certain time interval in millisecond -* -* @return On success: Effective interval set in mili-second -* On failure: 0 -* -*/ -/****************************************************************************/ -tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */ -); - -/****************************************************************************/ -/** -* @brief Configures a timer to run as a free running timer -* -* This function initializes a timer to run as a free running timer -* -* @return Timer resolution (count / sec) -* -*/ -/****************************************************************************/ -tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - uint32_t divider /* [ IN ] Dividing the clock frequency */ -) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Starts a timer -* -* This function starts a preconfigured timer -* -* @return -1 - On Failure -* 0 - On Success -*/ -/****************************************************************************/ -int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Stops a timer -* -* This function stops a running timer -* -* @return -1 - On Failure -* 0 - On Success -*/ -/****************************************************************************/ -int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Gets current timer count -* -* This function returns the current timer value -* -* @return Current downcounting timer value -* -*/ -/****************************************************************************/ -tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Gets timer count rate -* -* This function returns the number of counts per second -* -* @return Count rate -* -*/ -/****************************************************************************/ -tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Enables timer interrupt -* -* This function enables the timer interrupt -* -* @return N/A -* -*/ -/****************************************************************************/ -void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Disables timer interrupt -* -* This function disable the timer interrupt -* -* @return N/A -*/ -/****************************************************************************/ -void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Clears the interrupt -* -* This function clears the timer interrupt -* -* @return N/A -* -* @note -* Must be called under the context of ISR -*/ -/****************************************************************************/ -void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Gets the interrupt status -* -* This function returns timer interrupt status -* -* @return Interrupt status -*/ -/****************************************************************************/ -tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Indentifies a timer causing interrupt -* -* This functions returns a timer causing interrupt -* -* @return 0xFFFFFFFF : No timer causing an interrupt -* ! 0xFFFFFFFF : timer causing an interrupt -* @note -* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function -*/ -/****************************************************************************/ -tmrHw_ID_t tmrHw_getInterruptSource(void); - -/****************************************************************************/ -/** -* @brief Displays specific timer registers -* -* -* @return void -* -*/ -/****************************************************************************/ -void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */ - int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ -); - -/****************************************************************************/ -/** -* @brief Use a timer to perform a busy wait delay for a number of usecs. -* -* @return N/A -*/ -/****************************************************************************/ -void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */ - unsigned long usecs /* [ IN ] usec to delay */ -) __attribute__ ((section(".aramtext"))); - -#endif /* _TMRHW_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h index 161973385fa..39f09cb8920 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h @@ -17,9 +17,9 @@ /* ---- Include Files ----------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include /* ---- Public Constants and Types ---------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h index 03238c29900..830f323c00c 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h @@ -17,8 +17,8 @@ /* ---- Include Files ----------------------------------------------------- */ -#include -#include +#include +#include #include #include diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h index b162448f613..76d7531d1e1 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h @@ -24,7 +24,7 @@ #define CHIPCHW_REG_H #include -#include +#include #include #define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h index f1b68e26fa6..cabb7dab42b 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h @@ -30,8 +30,8 @@ extern "C" { /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include #include diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h new file mode 100644 index 00000000000..bde7faa49e7 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h @@ -0,0 +1,596 @@ +/***************************************************************************** +* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +/****************************************************************************/ +/** +* @file dmacHw.h +* +* @brief API definitions for low level DMA controller driver +* +*/ +/****************************************************************************/ +#ifndef _DMACHW_H +#define _DMACHW_H + +#include + +#include +#include + +/* Define DMA Channel ID using DMA controller number (m) and channel number (c). + + System specific channel ID should be defined as follows + + For example: + + #include + ... + #define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5) + #define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0) + #define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1) + #define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3) + #define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4) + ... + #define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4) + #define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5) + #define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6) + ... +*/ +#define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c) + +typedef enum { + dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */ + dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */ + dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */ + dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */ + dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */ + dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */ + dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */ + dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */ +} dmacHw_CHANNEL_PRIORITY_e; + +/* Source destination master interface */ +typedef enum { + dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */ + dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */ + dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */ + dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */ +} dmacHw_MASTER_INTERFACE_e; + +typedef enum { + dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */ + dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */ + dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */ + dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */ + dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */ + dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */ + dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */ + dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */ +} dmacHw_TRANSACTION_WIDTH_e; + +typedef enum { + dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */ + dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ + dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ + dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ + dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */ + dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ + dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ + dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ +} dmacHw_BURST_WIDTH_e; + +typedef enum { + dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */ + dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */ + dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */ + dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */ +} dmacHw_TRANSFER_TYPE_e; + +typedef enum { + dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */ + dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */ + dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */ +} dmacHw_TRANSFER_MODE_e; + +typedef enum { + dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */ + dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */ + dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */ + dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */ + dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */ + dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */ +} dmacHw_ADDRESS_UPDATE_MODE_e; + +typedef enum { + dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */ + dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */ +} dmacHw_FLOW_CONTROL_e; + +typedef enum { + dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */ + dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */ + dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */ +} dmacHw_TRANSFER_STATUS_e; + +typedef enum { + dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */ + dmacHw_INTERRUPT_ENABLE /* Interrupt enable */ +} dmacHw_INTERRUPT_e; + +typedef enum { + dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */ + dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */ + dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */ + dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */ +} dmacHw_INTERRUPT_STATUS_e; + +typedef enum { + dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */ + dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */ + dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */ + dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */ + dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */ +} dmacHw_CONTROLLER_ATTRIB_e; + +typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */ +typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using + "dmacHw_MAKE_CHANNEL_ID" macro + */ +/* DMA channel configuration parameters */ +typedef struct { + uint32_t srcPeripheralPort; /* Source peripheral port */ + uint32_t dstPeripheralPort; /* Destination peripheral port */ + uint32_t srcStatusRegisterAddress; /* Source status register address */ + uint32_t dstStatusRegisterAddress; /* Destination status register address of type */ + + uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */ + uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */ + uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */ + uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */ + uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor. + 0 = Maximum possible. + */ + + dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */ + dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */ + dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */ + dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */ + dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */ + dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */ + dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */ + dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */ + dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */ + dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */ + dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */ + dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */ + dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */ + dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */ + dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */ +} dmacHw_CONFIG_t; + +/****************************************************************************/ +/** +* @brief Initializes DMA +* +* This function initializes DMA CSP driver +* +* @note +* Must be called before using any DMA channel +*/ +/****************************************************************************/ +void dmacHw_initDma(void); + +/****************************************************************************/ +/** +* @brief Exit function for DMA +* +* This function isolates DMA from the system +* +*/ +/****************************************************************************/ +void dmacHw_exitDma(void); + +/****************************************************************************/ +/** +* @brief Gets a handle to a DMA channel +* +* This function returns a handle, representing a control block of a particular DMA channel +* +* @return -1 - On Failure +* handle - On Success, representing a channel control block +* +* @note +* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro +*/ +/****************************************************************************/ +dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */ + ); + +/****************************************************************************/ +/** +* @brief Initializes a DMA channel for use +* +* This function initializes and resets a DMA channel for use +* +* @return -1 - On Failure +* 0 - On Success +* +* @note +* None +*/ +/****************************************************************************/ +int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ + ); + +/****************************************************************************/ +/** +* @brief Estimates number of descriptor needed to perform certain DMA transfer +* +* +* @return On failure : -1 +* On success : Number of descriptor count +* +* +*/ +/****************************************************************************/ +int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ + void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ + void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ + size_t dataLen /* [ IN ] Data length in bytes */ + ); + +/****************************************************************************/ +/** +* @brief Initializes descriptor ring +* +* This function will initializes the descriptor ring of a DMA channel +* +* +* @return -1 - On failure +* 0 - On success +* @note +* - "len" parameter should be obtained from "dmacHw_descriptorLen" +* - Descriptor buffer MUST be 32 bit aligned and uncached as it +* is accessed by ARM and DMA +*/ +/****************************************************************************/ +int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */ + uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */ + uint32_t len, /* [ IN ] Size of the pBuf */ + uint32_t num /* [ IN ] Number of descriptor in the ring */ + ); + +/****************************************************************************/ +/** +* @brief Finds amount of memory required to form a descriptor ring +* +* +* @return Number of bytes required to form a descriptor ring +* +* +* @note +* None +*/ +/****************************************************************************/ +uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */ + ); + +/****************************************************************************/ +/** +* @brief Configure DMA channel +* +* @return 0 : On success +* -1 : On failure +*/ +/****************************************************************************/ +int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ + dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */ + ); + +/****************************************************************************/ +/** +* @brief Set descriptors for known data length +* +* When DMA has to work as a flow controller, this function prepares the +* descriptor chain to transfer data +* +* from: +* - Memory to memory +* - Peripheral to memory +* - Memory to Peripheral +* - Peripheral to Peripheral +* +* @return -1 - On failure +* 0 - On success +* +*/ +/****************************************************************************/ +int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ + void *pDescriptor, /* [ IN ] Descriptor buffer */ + void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ + void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ + size_t dataLen /* [ IN ] Length in bytes */ + ); + +/****************************************************************************/ +/** +* @brief Indicates whether DMA transfer is in progress or completed +* +* @return DMA transfer status +* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing +* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed +* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error +* +*/ +/****************************************************************************/ +dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ + ); + +/****************************************************************************/ +/** +* @brief Set descriptor carrying control information +* +* This function will be used to send specific control information to the device +* using the DMA channel +* +* +* @return -1 - On failure +* 0 - On success +* +* @note +* None +*/ +/****************************************************************************/ +int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ + void *pDescriptor, /* [ IN ] Descriptor buffer */ + uint32_t ctlAddress, /* [ IN ] Address of the device control register */ + uint32_t control /* [ IN ] Device control information */ + ); + +/****************************************************************************/ +/** +* @brief Read data DMA transferred to memory +* +* This function will read data that has been DMAed to memory while transferring from: +* - Memory to memory +* - Peripheral to memory +* +* @return 0 - No more data is available to read +* 1 - More data might be available to read +* +*/ +/****************************************************************************/ +int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ + dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ + void *pDescriptor, /* [ IN ] Descriptor buffer */ + void **ppBbuf, /* [ OUT ] Data received */ + size_t *pLlen /* [ OUT ] Length of the data received */ + ); + +/****************************************************************************/ +/** +* @brief Prepares descriptor ring, when source peripheral working as a flow controller +* +* This function will form the descriptor ring by allocating buffers, when source peripheral +* has to work as a flow controller to transfer data from: +* - Peripheral to memory. +* +* @return -1 - On failure +* 0 - On success +* +* +* @note +* None +*/ +/****************************************************************************/ +int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ + dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ + void *pDescriptor, /* [ IN ] Descriptor buffer */ + uint32_t srcAddr, /* [ IN ] Source peripheral address */ + void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */ + int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */ + int num /* [ IN ] Number of descriptor to set */ + ); + +/****************************************************************************/ +/** +* @brief Program channel register to initiate transfer +* +* @return void +* +* +* @note +* - Descriptor buffer MUST ALWAYS be flushed before calling this function +* - This function should also be called from ISR to program the channel with +* pending descriptors +*/ +/****************************************************************************/ +void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ + dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ + void *pDescriptor /* [ IN ] Descriptor buffer */ + ); + +/****************************************************************************/ +/** +* @brief Resets descriptor control information +* +* @return void +*/ +/****************************************************************************/ +void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */ + ); + +/****************************************************************************/ +/** +* @brief Program channel register to stop transfer +* +* Ensures the channel is not doing any transfer after calling this function +* +* @return void +* +*/ +/****************************************************************************/ +void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ + ); + +/****************************************************************************/ +/** +* @brief Check the existence of pending descriptor +* +* This function confirmes if there is any pending descriptor in the chain +* to program the channel +* +* @return 1 : Channel need to be programmed with pending descriptor +* 0 : No more pending descriptor to programe the channel +* +* @note +* - This function should be called from ISR in case there are pending +* descriptor to program the channel. +* +* Example: +* +* dmac_isr () +* { +* ... +* if (dmacHw_descriptorPending (handle)) +* { +* dmacHw_initiateTransfer (handle); +* } +* } +* +*/ +/****************************************************************************/ +uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ + void *pDescriptor /* [ IN ] Descriptor buffer */ + ); + +/****************************************************************************/ +/** +* @brief Deallocates source or destination memory, allocated +* +* This function can be called to deallocate data memory that was DMAed successfully +* +* @return -1 - On failure +* 0 - On success +* +* @note +* This function will be called ONLY, when source OR destination address is pointing +* to dynamic memory +*/ +/****************************************************************************/ +int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ + void *pDescriptor, /* [ IN ] Descriptor buffer */ + void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */ + ); + +/****************************************************************************/ +/** +* @brief Clears the interrupt +* +* This function clears the DMA channel specific interrupt +* +* @return N/A +* +* @note +* Must be called under the context of ISR +*/ +/****************************************************************************/ +void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ + ); + +/****************************************************************************/ +/** +* @brief Returns the cause of channel specific DMA interrupt +* +* This function returns the cause of interrupt +* +* @return Interrupt status, each bit representing a specific type of interrupt +* of type dmacHw_INTERRUPT_STATUS_e +* @note +* This function should be called under the context of ISR +*/ +/****************************************************************************/ +dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ + ); + +/****************************************************************************/ +/** +* @brief Indentifies a DMA channel causing interrupt +* +* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e +* +* @return NULL : No channel causing DMA interrupt +* ! NULL : Handle to a channel causing DMA interrupt +* @note +* dmacHw_clearInterrupt() must be called with a valid handle after calling this function +*/ +/****************************************************************************/ +dmacHw_HANDLE_t dmacHw_getInterruptSource(void); + +/****************************************************************************/ +/** +* @brief Sets channel specific user data +* +* This function associates user data to a specific DMA channel +* +*/ +/****************************************************************************/ +void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ + void *userData /* [ IN ] User data */ + ); + +/****************************************************************************/ +/** +* @brief Gets channel specific user data +* +* This function returns user data specific to a DMA channel +* +* @return user data +*/ +/****************************************************************************/ +void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ + ); + +/****************************************************************************/ +/** +* @brief Displays channel specific registers and other control parameters +* +* +* @return void +* +* @note +* None +*/ +/****************************************************************************/ +void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ + void *pDescriptor, /* [ IN ] Descriptor buffer */ + int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ + ); + +/****************************************************************************/ +/** +* @brief Provides DMA controller attributes +* +* +* @return DMA controller attributes +* +* @note +* None +*/ +/****************************************************************************/ +uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ + dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */ + ); + +#endif /* _DMACHW_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h index d67e2f8c22d..9d9455e0c39 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_PRIV_H #define _DMACHW_PRIV_H -#include +#include /* Data type for DMA Link List Item */ typedef struct { diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h index f1ecf96f2da..1be9556ba14 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_REG_H #define _DMACHW_REG_H -#include +#include #include /* Data type for 64 bit little endian register */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index 0aeb6a6fe7f..49403d5725e 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -27,8 +27,8 @@ #define _INTCHW_REG_H /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include #include /* ---- Public Constants and Types --------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/reg.h b/arch/arm/mach-bcmring/include/mach/csp/reg.h new file mode 100644 index 00000000000..026eb0b3ba2 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/reg.h @@ -0,0 +1,114 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +/****************************************************************************/ +/** +* @file reg.h +* +* @brief Generic register definitions used in CSP +*/ +/****************************************************************************/ + +#ifndef CSP_REG_H +#define CSP_REG_H + +/* ---- Include Files ---------------------------------------------------- */ + +#include + +/* ---- Public Constants and Types --------------------------------------- */ + +#define __REG32(x) (*((volatile uint32_t *)(x))) +#define __REG16(x) (*((volatile uint16_t *)(x))) +#define __REG8(x) (*((volatile uint8_t *) (x))) + +/* Macros used to define a sequence of reserved registers. The start / end */ +/* are byte offsets in the particular register definition, with the "end" */ +/* being the offset of the next un-reserved register. E.g. if offsets */ +/* 0x10 through to 0x1f are reserved, then this reserved area could be */ +/* specified as follows. */ +/* typedef struct */ +/* { */ +/* uint32_t reg1; offset 0x00 */ +/* uint32_t reg2; offset 0x04 */ +/* uint32_t reg3; offset 0x08 */ +/* uint32_t reg4; offset 0x0c */ +/* REG32_RSVD(0x10, 0x20); */ +/* uint32_t reg5; offset 0x20 */ +/* ... */ +/* } EXAMPLE_REG_t; */ +#define REG8_RSVD(start, end) uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)] +#define REG16_RSVD(start, end) uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)] +#define REG32_RSVD(start, end) uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)] + +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + +/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */ +/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the */ +/* flags variable to be declared locally. */ +/* e.g. */ +/* statement1; */ +/* { */ +/* REG_LOCAL_IRQ_SAVE; */ +/* */ +/* REG_LOCAL_IRQ_RESTORE; */ +/* } */ +/* statement2; */ +/* */ + +#if defined(__KERNEL__) && !defined(STANDALONE) +#include +#include + +#define REG_LOCAL_IRQ_SAVE HW_DECLARE_SPINLOCK(reg32) \ + unsigned long flags; HW_IRQ_SAVE(reg32, flags) + +#define REG_LOCAL_IRQ_RESTORE HW_IRQ_RESTORE(reg32, flags) + +#else + +#define REG_LOCAL_IRQ_SAVE +#define REG_LOCAL_IRQ_RESTORE + +#endif + +static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) +{ + REG_LOCAL_IRQ_SAVE; + *reg &= value; + REG_LOCAL_IRQ_RESTORE; +} + +static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) +{ + REG_LOCAL_IRQ_SAVE; + *reg |= value; + REG_LOCAL_IRQ_RESTORE; +} + +static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, + uint32_t value) +{ + REG_LOCAL_IRQ_SAVE; + *reg = (*reg & mask) | value; + REG_LOCAL_IRQ_RESTORE; +} + +static inline void reg32_write(volatile uint32_t *reg, uint32_t value) +{ + *reg = value; +} + +#endif /* CSP_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h new file mode 100644 index 00000000000..1cc882ae60f --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h @@ -0,0 +1,263 @@ +/***************************************************************************** +* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +/****************************************************************************/ +/** +* @file tmrHw.h +* +* @brief API definitions for low level Timer driver +* +*/ +/****************************************************************************/ +#ifndef _TMRHW_H +#define _TMRHW_H + +#include + +typedef uint32_t tmrHw_ID_t; /* Timer ID */ +typedef uint32_t tmrHw_COUNT_t; /* Timer count */ +typedef uint32_t tmrHw_INTERVAL_t; /* Timer interval */ +typedef uint32_t tmrHw_RATE_t; /* Timer event (count/interrupt) rate */ + +typedef enum { + tmrHw_INTERRUPT_STATUS_SET, /* Interrupted */ + tmrHw_INTERRUPT_STATUS_UNSET /* No Interrupt */ +} tmrHw_INTERRUPT_STATUS_e; + +typedef enum { + tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */ + tmrHw_CAPABILITY_RESOLUTION /* Timer resolution in bits */ +} tmrHw_CAPABILITY_e; + +/****************************************************************************/ +/** +* @brief Get timer capability +* +* This function returns various capabilities/attributes of a timer +* +* @return Numeric capability +* +*/ +/****************************************************************************/ +uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ + tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */ +); + +/****************************************************************************/ +/** +* @brief Configures a periodic timer in terms of timer interrupt rate +* +* This function initializes a periodic timer to generate specific number of +* timer interrupt per second +* +* @return On success: Effective timer frequency +* On failure: 0 +* +*/ +/****************************************************************************/ +tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ + tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */ +); + +/****************************************************************************/ +/** +* @brief Configures a periodic timer to generate timer interrupt after +* certain time interval +* +* This function initializes a periodic timer to generate timer interrupt +* after every time interval in millisecond +* +* @return On success: Effective interval set in mili-second +* On failure: 0 +* +*/ +/****************************************************************************/ +tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ + tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */ +); + +/****************************************************************************/ +/** +* @brief Configures a periodic timer to generate timer interrupt just once +* after certain time interval +* +* This function initializes a periodic timer to generate a single ticks after +* certain time interval in millisecond +* +* @return On success: Effective interval set in mili-second +* On failure: 0 +* +*/ +/****************************************************************************/ +tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ + tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */ +); + +/****************************************************************************/ +/** +* @brief Configures a timer to run as a free running timer +* +* This function initializes a timer to run as a free running timer +* +* @return Timer resolution (count / sec) +* +*/ +/****************************************************************************/ +tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ + uint32_t divider /* [ IN ] Dividing the clock frequency */ +) __attribute__ ((section(".aramtext"))); + +/****************************************************************************/ +/** +* @brief Starts a timer +* +* This function starts a preconfigured timer +* +* @return -1 - On Failure +* 0 - On Success +*/ +/****************************************************************************/ +int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ +) __attribute__ ((section(".aramtext"))); + +/****************************************************************************/ +/** +* @brief Stops a timer +* +* This function stops a running timer +* +* @return -1 - On Failure +* 0 - On Success +*/ +/****************************************************************************/ +int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ +); + +/****************************************************************************/ +/** +* @brief Gets current timer count +* +* This function returns the current timer value +* +* @return Current downcounting timer value +* +*/ +/****************************************************************************/ +tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */ +) __attribute__ ((section(".aramtext"))); + +/****************************************************************************/ +/** +* @brief Gets timer count rate +* +* This function returns the number of counts per second +* +* @return Count rate +* +*/ +/****************************************************************************/ +tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */ +) __attribute__ ((section(".aramtext"))); + +/****************************************************************************/ +/** +* @brief Enables timer interrupt +* +* This function enables the timer interrupt +* +* @return N/A +* +*/ +/****************************************************************************/ +void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ +); + +/****************************************************************************/ +/** +* @brief Disables timer interrupt +* +* This function disable the timer interrupt +* +* @return N/A +*/ +/****************************************************************************/ +void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ +); + +/****************************************************************************/ +/** +* @brief Clears the interrupt +* +* This function clears the timer interrupt +* +* @return N/A +* +* @note +* Must be called under the context of ISR +*/ +/****************************************************************************/ +void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ +); + +/****************************************************************************/ +/** +* @brief Gets the interrupt status +* +* This function returns timer interrupt status +* +* @return Interrupt status +*/ +/****************************************************************************/ +tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */ +); + +/****************************************************************************/ +/** +* @brief Indentifies a timer causing interrupt +* +* This functions returns a timer causing interrupt +* +* @return 0xFFFFFFFF : No timer causing an interrupt +* ! 0xFFFFFFFF : timer causing an interrupt +* @note +* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function +*/ +/****************************************************************************/ +tmrHw_ID_t tmrHw_getInterruptSource(void); + +/****************************************************************************/ +/** +* @brief Displays specific timer registers +* +* +* @return void +* +*/ +/****************************************************************************/ +void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */ + int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ +); + +/****************************************************************************/ +/** +* @brief Use a timer to perform a busy wait delay for a number of usecs. +* +* @return N/A +*/ +/****************************************************************************/ +void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */ + unsigned long usecs /* [ IN ] usec to delay */ +) __attribute__ ((section(".aramtext"))); + +#endif /* _TMRHW_H */ diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h index 72543781207..13e01384d6f 100644 --- a/arch/arm/mach-bcmring/include/mach/dma.h +++ b/arch/arm/mach-bcmring/include/mach/dma.h @@ -27,7 +27,7 @@ #include #include -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h index 387376ffb56..f8d51a8b0b1 100644 --- a/arch/arm/mach-bcmring/include/mach/reg_nand.h +++ b/arch/arm/mach-bcmring/include/mach/reg_nand.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_NAND_H /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h index 0992842caa7..041a68eb666 100644 --- a/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_UMI_H /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c index af9c3d7e2a0..59412903466 100644 --- a/arch/arm/mach-bcmring/timer.c +++ b/arch/arm/mach-bcmring/timer.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include /* The core.c file initializes timers 1 and 3 as a linux clocksource. */ -- cgit v1.2.3 From 878040ef831a12855af26a42cc25c817f4fb3f2d Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 25 Apr 2012 16:44:23 +0000 Subject: ARM: bcmring: use proper MMIO accessors A lot of code in bcmring just dereferences pointers to MMIO locations, which is not safe. This annotates the pointers correctly using __iomem and uses readl/write to access them. Signed-off-by: Arnd Bergmann --- arch/arm/mach-bcmring/csp/chipc/chipcHw.c | 127 +++++++++++---------- arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c | 80 ++++++------- arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c | 11 +- arch/arm/mach-bcmring/csp/dmac/dmacHw.c | 21 ++-- arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c | 2 +- .../mach-bcmring/include/mach/csp/chipcHw_inline.h | 115 ++++++++++--------- .../mach-bcmring/include/mach/csp/chipcHw_reg.h | 4 +- arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h | 2 +- arch/arm/mach-bcmring/include/mach/csp/dmacHw.h | 2 +- .../arm/mach-bcmring/include/mach/csp/dmacHw_reg.h | 104 ++++++++--------- .../arm/mach-bcmring/include/mach/csp/intcHw_reg.h | 14 +-- arch/arm/mach-bcmring/include/mach/csp/mm_io.h | 6 +- arch/arm/mach-bcmring/include/mach/csp/reg.h | 23 ++-- .../mach-bcmring/include/mach/csp/secHw_inline.h | 10 +- arch/arm/mach-bcmring/include/mach/reg_umi.h | 2 +- arch/arm/mach-bcmring/mm.c | 4 +- drivers/mtd/nand/bcm_umi_nand.c | 12 +- drivers/mtd/nand/nand_bcm_umi.h | 71 ++++++------ 18 files changed, 306 insertions(+), 304 deletions(-) diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c index 5ac7e250972..5050833817b 100644 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c @@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom) /****************************************************************************/ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ ) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; - volatile uint32_t *pDependentClock = (uint32_t *) 0x0; + uint32_t __iomem *pPLLReg = NULL; + uint32_t __iomem *pClockCtrl = NULL; + uint32_t __iomem *pDependentClock = NULL; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ uint32_t dependentClockType = 0; uint32_t vcoHz = 0; /* Get VCO frequencies */ - if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur } else { vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur if (pPLLReg) { /* Obtain PLL clock frequency */ - if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (clock == chipcHw_CLOCK_DDR) { /* DDR frequency is configured in PLLDivider register */ - return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); + return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { vcoHz >>= 1; } /* Obtain PLL clock frequency using VCO dividers */ - return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } } else if (pClockCtrl) { /* Obtain divider clock frequency */ uint32_t div; uint32_t freq = 0; - if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (pDependentClock) { /* Identify the dependent clock frequency */ switch (dependentClockType) { case PLL_CLOCK: - if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent PLL clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain PLL clock frequency using VCO dividers */ - div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK; + div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK; freq = div ? chipcHw_divide(vcoHz, div) : 0; } break; case NON_PLL_CLOCK: - if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { + if (pDependentClock == &pChipcHw->ACLKClock) { freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent divider clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain divider clock frequency using XTAL dividers */ - div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256)); } } @@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur freq = chipcHw_XTAL_FREQ_Hz; } - div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK; return chipcHw_divide(freq, (div ? div : 256)); } return 0; @@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ uint32_t freq /* [ IN ] Clock frequency in Hz */ ) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; - volatile uint32_t *pDependentClock = (uint32_t *) 0x0; + uint32_t __iomem *pPLLReg = NULL; + uint32_t __iomem *pClockCtrl = NULL; + uint32_t __iomem *pDependentClock = NULL; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ @@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu uint32_t desVcoHz = 0; /* Get VCO frequencies */ - if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Desired VCO frequency */ desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1); } else { vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -307,8 +307,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu { REG_LOCAL_IRQ_SAVE; /* Dvide DDR_phy by two to obtain DDR_ctrl clock */ - pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) - << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); + writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->DDRClock; @@ -329,8 +328,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Configure the VPM:BUS ratio settings */ { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) - << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); + writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->VPMClock; @@ -428,9 +426,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* For DDR settings use only the PLL divider clock */ if (pPLLReg == &pChipcHw->DDRClock) { /* Set M1DIV for PLL1, which controls the DDR clock */ - reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); + reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); + freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { @@ -441,7 +439,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK)); reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } /* Wait for for atleast 200ns as per the protocol to change frequency */ udelay(1); @@ -460,16 +458,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (pDependentClock) { switch (dependentClockType) { case PLL_CLOCK: - divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); + divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); break; case NON_PLL_CLOCK: { uint32_t sourceClock = 0; - if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { + if (pDependentClock == &pChipcHw->ACLKClock) { sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; + uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256)); } divider = chipcHw_divide(sourceClock, freq); @@ -483,7 +481,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (divider) { REG_LOCAL_IRQ_SAVE; /* Set the divider to obtain the required frequency */ - *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK); + writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl); REG_LOCAL_IRQ_RESTORE; return freq; } @@ -515,25 +513,26 @@ static int vpmPhaseAlignA0(void) int count = 0; for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) { - phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; + phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; phaseValue = 0; prevPhaseComp = 0; /* Step 1: Look for falling PH_COMP transition */ /* Read the contents of VPM Clock resgister */ - phaseValue = pChipcHw->VPMClock; + phaseValue = readl(&pChipcHw->VPMClock); do { /* Store previous value of phase comparator */ prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); /* Read the contents of VPM Clock resgister. */ - phaseValue = pChipcHw->VPMClock; + phaseValue = readl(&pChipcHw->VPMClock); if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -557,12 +556,13 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl + 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + phaseValue = readl(&pChipcHw->VPMClock); /* Count number of adjustment made */ adjustCount++; } @@ -581,12 +581,13 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + phaseValue = readl(&pChipcHw->VPMClock); /* Count number of adjustment made */ adjustCount++; } @@ -605,12 +606,13 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + phaseValue = readl(&pChipcHw->VPMClock); /* Count number of adjustment made */ adjustCount++; } @@ -631,14 +633,14 @@ static int vpmPhaseAlignA0(void) /* Store previous value of phase comparator */ prevPhaseComp = phaseValue; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= - chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); /* Read the contents of VPM Clock resgister. */ - phaseValue = pChipcHw->VPMClock; + phaseValue = readl(&pChipcHw->VPMClock); if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -661,13 +663,13 @@ static int vpmPhaseAlignA0(void) } /* For VPM Phase should be perfectly aligned. */ - phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); + phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT); + writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock); /* Load new phase value */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); REG_LOCAL_IRQ_RESTORE; } @@ -697,7 +699,7 @@ int chipcHw_vpmPhaseAlign(void) int adjustCount = 0; /* Disable VPM access */ - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; + writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); /* Disable HW VPM phase alignment */ chipcHw_vpmHwPhaseAlignDisable(); /* Enable SW VPM phase alignment */ @@ -715,23 +717,24 @@ int chipcHw_vpmPhaseAlign(void) phaseControl--; } else { /* Enable VPM access */ - pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; + writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); /* Return adjust count */ return adjustCount; } /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); /* Count adjustment */ adjustCount++; } } /* Disable VPM access */ - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; + writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); return -1; } diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c index a711d9bdf31..8377d805416 100644 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c @@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig2 = - chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET, + &pChipcHw->PLLConfig2); pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | @@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); /* Enable CHIPC registers to control the PLL */ - pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; + writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); /* Set pre divider to get desired VCO frequency */ - pChipcHw->PLLPreDivider2 = pllPreDivider2; + writel(pllPreDivider2, &pChipcHw->PLLPreDivider2); /* Set NDIV Frac */ - pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; + writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2); /* This has to be removed once the default values are fixed for PLL2. */ - pChipcHw->PLLControl12 = 0x38000700; - pChipcHw->PLLControl22 = 0x00000015; + writel(0x38000700, &pChipcHw->PLLControl12); + writel(0x00000015, &pChipcHw->PLLControl22); /* Reset PLL2 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig2); } else { - pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig2); } REG_LOCAL_IRQ_RESTORE; } @@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - pChipcHw->PLLConfig2 &= + writel(readl(&pChipcHw->PLLConfig2) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN); + chipcHw_REG_PLL_CONFIG_POWER_DOWN), + &pChipcHw->PLLConfig2); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) ; { REG_LOCAL_IRQ_SAVE; /* Remove digital reset */ - pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET; + writel(readl(&pChipcHw->PLLConfig2) & + ~chipcHw_REG_PLL_CONFIG_D_RESET, + &pChipcHw->PLLConfig2); REG_LOCAL_IRQ_RESTORE; } @@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig = - chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET, + &pChipcHw->PLLConfig); /* Setting VCO frequency */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { pllPreDivider = @@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) } /* Enable CHIPC registers to control the PLL */ - pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; + writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); /* Set pre divider to get desired VCO frequency */ - pChipcHw->PLLPreDivider = pllPreDivider; + writel(pllPreDivider, &pChipcHw->PLLPreDivider); /* Set NDIV Frac */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { - pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | - chipcHw_REG_PLL_DIVIDER_NDIV_f_SS; + writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider); } else { - pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | - chipcHw_REG_PLL_DIVIDER_NDIV_f; + writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider); } /* Reset PLL1 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); } else { - pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); } REG_LOCAL_IRQ_RESTORE; @@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - pChipcHw->PLLConfig &= - ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN); + writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED) - || !(pChipcHw-> - PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED) + || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) ; /* Remove digital reset */ { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET; + writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig); REG_LOCAL_IRQ_RESTORE; } } @@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initializ chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET); /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */ - pChipcHw->ACLKClock = - (pChipcHw-> - ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> - armBusRatio & - chipcHw_REG_ACLKClock_CLK_DIV_MASK); + writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock); /* Set various core component frequencies. The order in which this is done is important for some. */ /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */ diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c index 74d2b023dce..f95ce913fa1 100644 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c @@ -50,15 +50,16 @@ void chipcHw_reset(uint32_t mask) chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); } /* Bypass the PLL clocks before reboot */ - pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; - pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; + writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, + &pChipcHw->UARTClock); + writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, + &pChipcHw->SPIClock); /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */ do { - ((uint32_t *) MM_IO_BASE_ARAM)[i] = - ((uint32_t *) &chipcHw_reset_run_from_aram)[i]; + writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i); i++; - } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ + } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ flush_cache_all(); diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c index 570ab0ab923..547f746c7ff 100644 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c @@ -27,7 +27,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include #include -#include +#include #include #include @@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handl ) { uint32_t val = 0; dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - dmacHw_MISC_t *pMiscReg = - (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module); + dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module); switch (pCblk->channel) { case 0: - val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28; break; case 1: - val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28; break; case 2: - val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28; break; case 3: - val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28; break; case 4: - val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28; break; case 5: - val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28; break; case 6: - val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28; break; case 7: - val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28; break; } diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c index ea0bd642b36..fe438699d11 100644 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c @@ -27,7 +27,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include -#include +#include #include #include diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h index 830f323c00c..a66f3f7abb8 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h @@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, /****************************************************************************/ static inline uint32_t chipcHw_getChipId(void) { - return pChipcHw->ChipId; + return readl(&pChipcHw->ChipId); } /****************************************************************************/ @@ -59,15 +59,16 @@ static inline uint32_t chipcHw_getChipId(void) /****************************************************************************/ static inline void chipcHw_enableSpreadSpectrum(void) { - if ((pChipcHw-> - PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != + if ((readl(&pChipcHw-> + PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { - ddrcReg_PHY_ADDR_CTL_REGP->ssCfg = - (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | + writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK << - ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT); - ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |= - ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; + ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT), + &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg); + writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) | + ddrcReg_PHY_ADDR_SS_CTRL_ENABLE, + &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl); } } @@ -93,8 +94,8 @@ static inline void chipcHw_disableSpreadSpectrum(void) /****************************************************************************/ static inline uint32_t chipcHw_getChipProductId(void) { - return (pChipcHw-> - ChipId & chipcHw_REG_CHIPID_BASE_MASK) >> + return (readl(&pChipcHw-> + ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >> chipcHw_REG_CHIPID_BASE_SHIFT; } @@ -109,7 +110,7 @@ static inline uint32_t chipcHw_getChipProductId(void) /****************************************************************************/ static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void) { - return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK; + return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK; } /****************************************************************************/ @@ -156,7 +157,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getBusInterfaceClockStatus(void) { - return pChipcHw->BusIntfClock; + return readl(&pChipcHw->BusIntfClock); } /****************************************************************************/ @@ -215,8 +216,9 @@ static inline void chipcHw_softResetDisable(uint64_t mask) /* Deassert module soft reset */ REG_LOCAL_IRQ_SAVE; - pChipcHw->SoftReset1 ^= ctrl1; - pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); + writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1); + writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 & + (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); REG_LOCAL_IRQ_RESTORE; } @@ -227,9 +229,10 @@ static inline void chipcHw_softResetEnable(uint64_t mask) uint32_t unhold = 0; REG_LOCAL_IRQ_SAVE; - pChipcHw->SoftReset1 |= ctrl1; + writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1); /* Mask out unhold request bits */ - pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); + writel(readl(&pChipcHw->SoftReset2) | (ctrl2 & + (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); /* Process unhold requests */ if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) { @@ -246,7 +249,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask) if (unhold) { /* Make sure unhold request is effective */ - pChipcHw->SoftReset1 &= ~unhold; + writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1); } REG_LOCAL_IRQ_RESTORE; } @@ -307,7 +310,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getStickyBits(void) { - return pChipcHw->Sticky; + return readl(&pChipcHw->Sticky); } /****************************************************************************/ @@ -328,7 +331,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_POR_BROM; } else { uint32_t sticky; - sticky = pChipcHw->Sticky; + sticky = readl(pChipcHw->Sticky); if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) { @@ -355,7 +358,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_GENERAL_5; } } - pChipcHw->Sticky = bits; + writel(bits, pChipcHw->Sticky); REG_LOCAL_IRQ_RESTORE; } @@ -377,7 +380,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 | chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 | chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) { - uint32_t sticky = pChipcHw->Sticky; + uint32_t sticky = readl(&pChipcHw->Sticky); if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) { @@ -410,7 +413,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) mask &= ~chipcHw_REG_STICKY_GENERAL_5; } } - pChipcHw->Sticky = bits | mask; + writel(bits | mask, &pChipcHw->Sticky); REG_LOCAL_IRQ_RESTORE; } @@ -426,7 +429,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getSoftStraps(void) { - return pChipcHw->SoftStraps; + return readl(&pChipcHw->SoftStraps); } /****************************************************************************/ @@ -456,7 +459,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions) /****************************************************************************/ static inline uint32_t chipcHw_getPinStraps(void) { - return pChipcHw->PinStraps; + return readl(&pChipcHw->PinStraps); } /****************************************************************************/ @@ -671,9 +674,9 @@ static inline void chipcHw_selectGE3(void) /****************************************************************************/ static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin) { - return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) & + return (readl(chipcHw_REG_GPIO_MUX(pin))) & (chipcHw_REG_GPIO_MUX_MASK << - chipcHw_REG_GPIO_MUX_POSITION(pin))) >> + chipcHw_REG_GPIO_MUX_POSITION(pin)) >> chipcHw_REG_GPIO_MUX_POSITION(pin); } @@ -841,8 +844,8 @@ static inline void chipcHw_setUsbDevice(void) static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, chipcHw_OPTYPE_e type, int mode) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; + uint32_t __iomem *pPLLReg = NULL; + uint32_t __iomem *pClockCtrl = NULL; switch (clock) { case chipcHw_CLOCK_DDR: @@ -1071,7 +1074,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock) /****************************************************************************/ static inline int chipcHw_isSoftwareStrapsEnable(void) { - return pChipcHw->SoftStraps & 0x00000001; + return readl(&pChipcHw->SoftStraps) & 0x00000001; } /****************************************************************************/ @@ -1138,7 +1141,7 @@ static inline void chipcHw_pll2TestDisable(void) /****************************************************************************/ static inline int chipcHw_isPllTestEnable(void) { - return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1147,7 +1150,7 @@ static inline int chipcHw_isPllTestEnable(void) /****************************************************************************/ static inline int chipcHw_isPll2TestEnable(void) { - return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1183,8 +1186,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val) /****************************************************************************/ static inline uint8_t chipcHw_getPllTestSelected(void) { - return (uint8_t) ((pChipcHw-> - PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((readl(&pChipcHw-> + PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1194,8 +1197,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void) /****************************************************************************/ static inline uint8_t chipcHw_getPll2TestSelected(void) { - return (uint8_t) ((pChipcHw-> - PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((readl(&pChipcHw-> + PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1208,7 +1211,8 @@ static inline uint8_t chipcHw_getPll2TestSelected(void) static inline void chipcHw_pll1Disable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig); REG_LOCAL_IRQ_RESTORE; } @@ -1221,7 +1225,8 @@ static inline void chipcHw_pll1Disable(void) static inline void chipcHw_pll2Disable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig2); REG_LOCAL_IRQ_RESTORE; } @@ -1233,7 +1238,8 @@ static inline void chipcHw_pll2Disable(void) static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; + writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, + &pChipcHw->Spare1); REG_LOCAL_IRQ_RESTORE; } @@ -1245,7 +1251,8 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) static inline void chipcHw_ddrPhaseAlignInterruptDisable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; + writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, + &pChipcHw->Spare1); REG_LOCAL_IRQ_RESTORE; } @@ -1333,7 +1340,8 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void) static inline void chipcHw_vpmSwPhaseAlignEnable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; + writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE, + &pChipcHw->VPMPhaseCtrl1); REG_LOCAL_IRQ_RESTORE; } @@ -1372,7 +1380,8 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void) static inline void chipcHw_vpmHwPhaseAlignDisable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; + writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE, + &pChipcHw->VPMPhaseCtrl1); REG_LOCAL_IRQ_RESTORE; } @@ -1474,8 +1483,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin) /****************************************************************************/ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1488,8 +1497,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1500,8 +1509,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> chipcHw_REG_DDR_PHASE_STATUS_SHIFT; } @@ -1513,8 +1522,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> chipcHw_REG_VPM_PHASE_STATUS_SHIFT; } @@ -1526,8 +1535,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrPhaseControl(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> chipcHw_REG_DDR_PHASE_CTRL_SHIFT; } @@ -1539,8 +1548,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmPhaseControl(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> chipcHw_REG_VPM_PHASE_CTRL_SHIFT; } diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h index 76d7531d1e1..26f5d0e4e1d 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h @@ -131,8 +131,8 @@ typedef struct { uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ } chipcHw_REG_t; -#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) -#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) +#define pChipcHw ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS) +#define pChipcPhysical (MM_ADDR_IO_CHIPC) #define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 #define chipcHw_REG_CHIPID_BASE_SHIFT 12 diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h index cabb7dab42b..39da2c1fdaf 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h @@ -416,7 +416,7 @@ extern "C" { } ddrcReg_PHY_ADDR_CTL_REG_t; #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400 -#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) +#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) /* @todo These SS definitions are duplicates of ones below */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h index bde7faa49e7..9dc90f46a84 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h @@ -23,7 +23,7 @@ #ifndef _DMACHW_H #define _DMACHW_H -#include +#include #include #include diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h index 1be9556ba14..7cd0aafa6f6 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h @@ -121,75 +121,75 @@ typedef struct { } dmacHw_MISC_t; /* Base registers */ -#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ -#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ +#define dmacHw_0_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ +#define dmacHw_1_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ extern uint32_t dmaChannelCount_0; extern uint32_t dmaChannelCount_1; /* Define channel specific registers */ -#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) +#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) /* Raw interrupt status registers */ -#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) -#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) -#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) -#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) -#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) -#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) +#define dmacHw_REG_INT_RAW_BASE(module) ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) +#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) +#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) +#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) +#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) +#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) -#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) -#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) -#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) -#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) -#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) +#define dmacHw_REG_INT_STAT_BASE(module) ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) +#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) +#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) +#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) +#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) +#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) -#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) -#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) -#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) -#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) -#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) +#define dmacHw_REG_INT_MASK_BASE(module) ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) +#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) +#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) +#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) +#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) +#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) /* Interrupt clear registers */ -#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) -#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) -#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) -#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) -#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) -#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) -#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) +#define dmacHw_REG_INT_CLEAR_BASE(module) ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) +#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) +#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) +#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) +#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) +#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) +#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) /* Software handshaking registers */ -#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) -#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) +#define dmacHw_REG_SW_HS_BASE(module) ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) +#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) /* Miscellaneous registers */ -#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) -#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) -#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) -#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) -#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) -#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) -#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) -#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) -#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) -#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) -#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) -#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) -#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) -#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) -#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) +#define dmacHw_REG_MISC_BASE(module) ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) +#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) +#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) +#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) +#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) +#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) +#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) +#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) +#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) +#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) +#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) +#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) +#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) +#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) +#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) /* Channel control registers */ #define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo) diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index 49403d5725e..f59db25b563 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -37,9 +37,9 @@ #define INTCHW_NUM_INTC 3 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ -#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) -#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) -#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) +#define INTCHW_INTC0 (MM_IO_BASE_INTC0) +#define INTCHW_INTC1 (MM_IO_BASE_INTC1) +#define INTCHW_SINTC (MM_IO_BASE_SINTC) /* INTC0 - interrupt controller 0 */ #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ @@ -232,15 +232,15 @@ /* ---- Public Variable Externs ------------------------------------------ */ /* ---- Public Function Prototypes --------------------------------------- */ /* Clear one or more IRQ interrupts. */ -static inline void intcHw_irq_disable(void *basep, uint32_t mask) +static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask) { - __REG32(basep + INTCHW_INTENCLEAR) = mask; + writel(mask, basep + INTCHW_INTENCLEAR); } /* Enables one or more IRQ interrupts. */ -static inline void intcHw_irq_enable(void *basep, uint32_t mask) +static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask) { - __REG32(basep + INTCHW_INTENABLE) = mask; + writel(mask, basep + INTCHW_INTENABLE); } #endif /* _INTCHW_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h index dbc98ddaeb6..47450c23685 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h +++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h @@ -49,7 +49,7 @@ #ifdef __ASSEMBLY__ #define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)) #else -#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ +#define MM_IO_PHYS_TO_VIRT(phys) (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))) #endif #endif @@ -60,8 +60,8 @@ #ifdef __ASSEMBLY__ #define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)) #else -#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ - ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))) +#define MM_IO_VIRT_TO_PHYS(virt) (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ + ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF))) #endif #endif diff --git a/arch/arm/mach-bcmring/include/mach/csp/reg.h b/arch/arm/mach-bcmring/include/mach/csp/reg.h index 026eb0b3ba2..d9cbdca8cd2 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/reg.h @@ -26,12 +26,13 @@ /* ---- Include Files ---------------------------------------------------- */ #include +#include /* ---- Public Constants and Types --------------------------------------- */ -#define __REG32(x) (*((volatile uint32_t *)(x))) -#define __REG16(x) (*((volatile uint16_t *)(x))) -#define __REG8(x) (*((volatile uint8_t *) (x))) +#define __REG32(x) (*((volatile uint32_t __iomem *)(x))) +#define __REG16(x) (*((volatile uint16_t __iomem *)(x))) +#define __REG8(x) (*((volatile uint8_t __iomem *) (x))) /* Macros used to define a sequence of reserved registers. The start / end */ /* are byte offsets in the particular register definition, with the "end" */ @@ -84,31 +85,31 @@ #endif -static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) +static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - *reg &= value; + __raw_writel(__raw_readl(reg) & value, reg); REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) +static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - *reg |= value; + __raw_writel(__raw_readl(reg) | value, reg); REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, +static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask, uint32_t value) { REG_LOCAL_IRQ_SAVE; - *reg = (*reg & mask) | value; + __raw_writel((__raw_readl(reg) & mask) | value, reg); REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_write(volatile uint32_t *reg, uint32_t value) +static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value) { - *reg = value; + __raw_writel(value, reg); } #endif /* CSP_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h index 9cd6a032ab7..55d3cd4fd1e 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h @@ -34,7 +34,7 @@ /****************************************************************************/ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; + secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; @@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK /****************************************************************************/ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; + secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { - regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF; + writel(mask & 0x0000FFFF, ®p->reg[secHw_IDX_LS].setUnsecure); } if (mask & 0xFFFF0000) { - regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16; + writel(mask >> 16, ®p->reg[secHw_IDX_MS].setUnsecure); } } @@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MA /****************************************************************************/ static inline uint32_t secHw_getStatus(void) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; + secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; return (regp->reg[1].status << 16) + regp->reg[0].status; } diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h index 041a68eb666..56dd9de7d83 100644 --- a/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h @@ -233,5 +233,5 @@ #define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 /* location within a page (512 byte) */ #define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 -#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) +#define REG_UMI_BCH_ERR_LOC_ADDR(index) (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) #endif diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c index 1adec78ec94..33824a81cac 100644 --- a/arch/arm/mach-bcmring/mm.c +++ b/arch/arm/mach-bcmring/mm.c @@ -20,12 +20,12 @@ #include #include -#define IO_DESC(va, sz) { .virtual = va, \ +#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_DEVICE } -#define MEM_DESC(va, sz) { .virtual = va, \ +#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_MEMORY } diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c index 6908cdde306..55e7799f4bf 100644 --- a/drivers/mtd/nand/bcm_umi_nand.c +++ b/drivers/mtd/nand/bcm_umi_nand.c @@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd) int bcm_umi_nand_inithw(void) { /* Configure nand timing parameters */ - REG_UMI_NAND_TCR &= ~0x7ffff; - REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR; + writel(readl(®_UMI_NAND_TCR) & ~0x7ffff, ®_UMI_NAND_TCR); + writel(readl(®_UMI_NAND_TCR) | HW_CFG_NAND_TCR, ®_UMI_NAND_TCR); #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS) /* enable software control of CS */ - REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL; + writel(readl(®_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, ®_UMI_NAND_TCR); #endif /* keep NAND chip select asserted */ - REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED; + writel(readl(®_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, ®_UMI_NAND_RCSR); - REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16; + writel(readl(®_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, ®_UMI_NAND_TCR); /* enable writes to flash */ - REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP; + writel(readl(®_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, ®_UMI_MMD_ICR); writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET); nand_bcm_umi_wait_till_ready(); diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h index a158d5dd9a0..d90186684db 100644 --- a/drivers/mtd/nand/nand_bcm_umi.h +++ b/drivers/mtd/nand/nand_bcm_umi.h @@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData, /* Check in device is ready */ static inline int nand_bcm_umi_dev_ready(void) { - return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY; + return readl(®_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY; } /* Wait until device is ready */ @@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void) static inline void nand_bcm_umi_hamming_enable_hwecc(void) { /* disable and reset ECC, 512 byte page */ - REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | - REG_UMI_NAND_ECC_CSR_256BYTE); + writel(readl(®_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | + REG_UMI_NAND_ECC_CSR_256BYTE), ®_UMI_NAND_ECC_CSR); /* enable ECC */ - REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE; + writel(readl(®_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE, + ®_UMI_NAND_ECC_CSR); } #if NAND_ECC_BCH @@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void) static inline void nand_bcm_umi_bch_enable_read_hwecc(void) { /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; + writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, ®_UMI_BCH_CTRL_STATUS); /* Turn on ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS); } /* Enable BCH Write ECC */ static inline void nand_bcm_umi_bch_enable_write_hwecc(void) { /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID; + writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, ®_UMI_BCH_CTRL_STATUS); /* Turn on ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, ®_UMI_BCH_CTRL_STATUS); } /* Config number of BCH ECC bytes */ @@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) uint32_t numBits = numEccBytes * 8; /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = - REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | - REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; + writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | + REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, + ®_UMI_BCH_CTRL_STATUS); /* Every correctible bit requires 13 ECC bits */ tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT); @@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT); /* Write the settings */ - REG_UMI_BCH_N = nValue; - REG_UMI_BCH_T = tValue; - REG_UMI_BCH_K = kValue; + writel(nValue, ®_UMI_BCH_N); + writel(tValue, ®_UMI_BCH_T); + writel(kValue, ®_UMI_BCH_K); } /* Pause during ECC read calculation to skip bytes in OOB */ static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void) { - REG_UMI_BCH_CTRL_STATUS = - REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | - REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, ®_UMI_BCH_CTRL_STATUS); } /* Resume during ECC read calculation after skipping bytes in OOB */ static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void) { - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS); } /* Poll read ECC calc to check when hardware completes */ @@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) do { /* wait for ECC to be valid */ - regVal = REG_UMI_BCH_CTRL_STATUS; + regVal = readl(®_UMI_BCH_CTRL_STATUS); } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0); return regVal; @@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void) { /* wait for ECC to be valid */ - while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) + while ((readl(®_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) == 0) ; } @@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, if (pageSize != NAND_DATA_ACCESS_SIZE) { /* skip BI */ #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; + *oobp++ = readb(®_NAND_DATA8); #else - REG_NAND_DATA8; + readb(®_NAND_DATA8); #endif numToRead--; } @@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, while (numToRead > numEccBytes) { /* skip free oob region */ #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; + *oobp++ = readb(®_NAND_DATA8); #else - REG_NAND_DATA8; + readb(®_NAND_DATA8); #endif numToRead--; } @@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, while (numToRead > 11) { #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp = REG_NAND_DATA8; + *oobp = readb(®_NAND_DATA8); eccCalc[eccPos++] = *oobp; oobp++; #else - eccCalc[eccPos++] = REG_NAND_DATA8; + eccCalc[eccPos++] = readb(®_NAND_DATA8); #endif numToRead--; } @@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, if (numToRead == 11) { /* read BI */ #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; + *oobp++ = readb(®_NAND_DATA8); #else - REG_NAND_DATA8; + readb(®_NAND_DATA8); #endif numToRead--; } @@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, nand_bcm_umi_bch_resume_read_ecc_calc(); while (numToRead) { #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp = REG_NAND_DATA8; + *oobp = readb(®_NAND_DATA8); eccCalc[eccPos++] = *oobp; oobp++; #else - eccCalc[eccPos++] = REG_NAND_DATA8; + eccCalc[eccPos++] = readb(®_NAND_DATA8); #endif numToRead--; } @@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, if (pageSize == NAND_DATA_ACCESS_SIZE) { /* Now fill in the ECC bytes */ if (numEccBytes >= 13) - eccVal = REG_UMI_BCH_WR_ECC_3; + eccVal = readl(®_UMI_BCH_WR_ECC_3); /* Usually we skip CM in oob[0,1] */ NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0], @@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC 12 */ if (numEccBytes >= 9) - eccVal = REG_UMI_BCH_WR_ECC_2; + eccVal = readl(®_UMI_BCH_WR_ECC_2); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3], (eccVal >> 24) & 0xff); /* ECC11 */ @@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, /* Now fill in the ECC bytes */ if (numEccBytes >= 13) - eccVal = REG_UMI_BCH_WR_ECC_3; + eccVal = readl(®_UMI_BCH_WR_ECC_3); /* Usually skip CM in oob[1,2] */ NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1], @@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC12 */ if (numEccBytes >= 9) - eccVal = REG_UMI_BCH_WR_ECC_2; + eccVal = readl(®_UMI_BCH_WR_ECC_2); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4], (eccVal >> 24) & 0xff); /* ECC11 */ @@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC8 */ if (numEccBytes >= 5) - eccVal = REG_UMI_BCH_WR_ECC_1; + eccVal = readl(®_UMI_BCH_WR_ECC_1); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8], (eccVal >> 24) & 0xff); /* ECC7 */ @@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC4 */ if (numEccBytes >= 1) - eccVal = REG_UMI_BCH_WR_ECC_0; + eccVal = readl(®_UMI_BCH_WR_ECC_0); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12], (eccVal >> 24) & 0xff); /* ECC3 */ -- cgit v1.2.3 From 67ac88ff10fa4253f716cb98ec43303f70711591 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 4 Jul 2012 14:14:16 -0500 Subject: i2c: iop3xx: clean-up trailing whitespace Remove a bunch of trailing whitespace. No functional changes. Signed-off-by: Rob Herring Cc: "Jean Delvare (PC drivers, core)" Cc: "Ben Dooks (embedded platforms)" Cc: "Wolfram Sang (embedded platforms)" Cc: linux-i2c@vger.kernel.org --- drivers/i2c/busses/i2c-iop3xx.c | 112 ++++++++++++++++++++-------------------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c index 93f147a96b6..567d87389e3 100644 --- a/drivers/i2c/busses/i2c-iop3xx.c +++ b/drivers/i2c/busses/i2c-iop3xx.c @@ -4,13 +4,13 @@ /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd * * - * With acknowledgements to i2c-algo-ibm_ocp.c by + * With acknowledgements to i2c-algo-ibm_ocp.c by * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com * * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund: * * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund - * + * * And which acknowledged Kyösti Mälkki , * Frodo Looijaard , Martin Bailey * @@ -45,8 +45,8 @@ /* global unit counter */ static int i2c_id; -static inline unsigned char -iic_cook_addr(struct i2c_msg *msg) +static inline unsigned char +iic_cook_addr(struct i2c_msg *msg) { unsigned char addr; @@ -55,24 +55,24 @@ iic_cook_addr(struct i2c_msg *msg) if (msg->flags & I2C_M_RD) addr |= 1; - return addr; + return addr; } -static void +static void iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap) { /* Follows devman 9.3 */ __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET); __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET); __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET); -} +} -static void +static void iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) { u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE; - /* + /* * Every time unit enable is asserted, GPOD needs to be cleared * on IOP3XX to avoid data corruption on the bus. */ @@ -86,7 +86,7 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) } #endif /* NB SR bits not same position as CR IE bits :-( */ - iop3xx_adap->SR_enabled = + iop3xx_adap->SR_enabled = IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD | IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY; @@ -96,23 +96,23 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); } -static void +static void iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap) { unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); - - cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | + + cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN); __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); } -/* - * NB: the handler has to clear the source of the interrupt! +/* + * NB: the handler has to clear the source of the interrupt! * Then it passes the SR flags of interest to BH via adap data */ -static irqreturn_t -iop3xx_i2c_irq_handler(int this_irq, void *dev_id) +static irqreturn_t +iop3xx_i2c_irq_handler(int this_irq, void *dev_id) { struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id; u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET); @@ -126,7 +126,7 @@ iop3xx_i2c_irq_handler(int this_irq, void *dev_id) } /* check all error conditions, clear them , report most important */ -static int +static int iop3xx_i2c_error(u32 sr) { int rc = 0; @@ -135,12 +135,12 @@ iop3xx_i2c_error(u32 sr) if ( !rc ) rc = -I2C_ERR_BERR; } if ((sr & IOP3XX_ISR_ALD)) { - if ( !rc ) rc = -I2C_ERR_ALD; + if ( !rc ) rc = -I2C_ERR_ALD; } - return rc; + return rc; } -static inline u32 +static inline u32 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap) { unsigned long flags; @@ -161,8 +161,8 @@ iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap) typedef int (* compare_func)(unsigned test, unsigned mask); /* returns 1 on correct comparison */ -static int -iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, +static int +iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, unsigned flags, unsigned* status, compare_func compare) { @@ -192,47 +192,47 @@ iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, } /* - * Concrete compare_funcs + * Concrete compare_funcs */ -static int +static int all_bits_clear(unsigned test, unsigned mask) { return (test & mask) == 0; } -static int +static int any_bits_set(unsigned test, unsigned mask) { return (test & mask) != 0; } -static int +static int iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) { - return iop3xx_i2c_wait_event( - iop3xx_adap, + return iop3xx_i2c_wait_event( + iop3xx_adap, IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, status, any_bits_set); } -static int +static int iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) { - return iop3xx_i2c_wait_event( - iop3xx_adap, + return iop3xx_i2c_wait_event( + iop3xx_adap, IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, status, any_bits_set); } -static int +static int iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) { - return iop3xx_i2c_wait_event( + return iop3xx_i2c_wait_event( iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear); } -static int -iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, +static int +iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, struct i2c_msg* msg) { unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); @@ -247,7 +247,7 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, } __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET); - + cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE; @@ -257,8 +257,8 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, return rc; } -static int -iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, +static int +iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, int stop) { unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); @@ -277,10 +277,10 @@ iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status); return rc; -} +} -static int -iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, +static int +iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, int stop) { unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); @@ -304,19 +304,19 @@ iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, return rc; } -static int +static int iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count) { struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; int ii; int rc = 0; - for (ii = 0; rc == 0 && ii != count; ++ii) + for (ii = 0; rc == 0 && ii != count; ++ii) rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1); return rc; } -static int +static int iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count) { struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; @@ -325,7 +325,7 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count) for (ii = 0; rc == 0 && ii != count; ++ii) rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1); - + return rc; } @@ -336,8 +336,8 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count) * Each transfer (i.e. a read or a write) is separated by a repeated start * condition. */ -static int -iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) +static int +iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) { struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; int rc; @@ -357,8 +357,8 @@ iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) /* * master_xfer() - main read/write entry */ -static int -iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, +static int +iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) { struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; @@ -375,14 +375,14 @@ iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, } iop3xx_i2c_transaction_cleanup(iop3xx_adap); - + if(ret) return ret; - return im; + return im; } -static u32 +static u32 iop3xx_i2c_func(struct i2c_adapter *adap) { return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; @@ -393,11 +393,11 @@ static const struct i2c_algorithm iop3xx_i2c_algo = { .functionality = iop3xx_i2c_func, }; -static int +static int iop3xx_i2c_remove(struct platform_device *pdev) { struct i2c_adapter *padapter = platform_get_drvdata(pdev); - struct i2c_algo_iop3xx_data *adapter_data = + struct i2c_algo_iop3xx_data *adapter_data = (struct i2c_algo_iop3xx_data *)padapter->algo_data; struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET); @@ -419,7 +419,7 @@ iop3xx_i2c_remove(struct platform_device *pdev) return 0; } -static int +static int iop3xx_i2c_probe(struct platform_device *pdev) { struct resource *res; -- cgit v1.2.3 From 701eb2647d7986b42fa973990649a83b3e15e8eb Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 4 Jul 2012 14:16:12 -0500 Subject: i2c: iop3xx: use standard gpiolib functions Instead of using the custom iop3xx gpio functions, use the gpiolib variants. This should be functionally the same since the gpiolib just calls the iop3xx gpio functions. This is needed in preparation of removing iop3xx mach/io.h headers. Signed-off-by: Rob Herring Cc: "Jean Delvare (PC drivers, core)" Cc: "Ben Dooks (embedded platforms)" Cc: "Wolfram Sang (embedded platforms)" Cc: linux-i2c@vger.kernel.org --- drivers/i2c/busses/i2c-iop3xx.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c index 567d87389e3..2f99613fd67 100644 --- a/drivers/i2c/busses/i2c-iop3xx.c +++ b/drivers/i2c/busses/i2c-iop3xx.c @@ -39,6 +39,7 @@ #include #include #include +#include #include "i2c-iop3xx.h" @@ -78,11 +79,11 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) */ #if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X) if (iop3xx_adap->id == 0) { - gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW); - gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW); + gpio_set_value(7, 0); + gpio_set_value(6, 0); } else { - gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW); - gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW); + gpio_set_value(5, 0); + gpio_set_value(4, 0); } #endif /* NB SR bits not same position as CR IE bits :-( */ -- cgit v1.2.3 From c2794437091a4fda72c4a4f3567dd728dcc0c3c9 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 29 Feb 2012 18:10:58 -0600 Subject: ARM: Add fixed PCI i/o mapping This adds a fixed virtual mapping for PCI i/o addresses. The mapping is located at the last 2MB of vmalloc region (0xfee00000-0xff000000). 2MB is used to align with PMD size, but IO_SPACE_LIMIT is 1MB. The space is reserved after .map_io and can be mapped at any time later with pci_ioremap_io. Platforms which need early i/o mapping (e.g. for vga console) can call pci_map_io_early in their .map_io function. This has changed completely from the 1st implementation which only supported creating the static mapping at .map_io. Signed-off-by: Rob Herring Cc: Russell King Acked-by: Nicolas Pitre --- Documentation/arm/memory.txt | 3 +++ arch/arm/include/asm/io.h | 8 ++++++ arch/arm/include/asm/mach/map.h | 8 ++++++ arch/arm/include/asm/mach/pci.h | 10 ++++++++ arch/arm/kernel/bios32.c | 13 ++++++++++ arch/arm/mm/ioremap.c | 14 +++++++++++ arch/arm/mm/mmu.c | 54 ++++++++++++++++++++++++++++++++--------- 7 files changed, 99 insertions(+), 11 deletions(-) diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt index 208a2d465b9..4bfb9ffbdbc 100644 --- a/Documentation/arm/memory.txt +++ b/Documentation/arm/memory.txt @@ -51,6 +51,9 @@ ffc00000 ffefffff DMA memory mapping region. Memory returned ff000000 ffbfffff Reserved for future expansion of DMA mapping region. +fee00000 feffffff Mapping of PCI I/O space. This is a static + mapping within the vmalloc space. + VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space. Memory returned by vmalloc/ioremap will be dynamically placed in this region. diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 815c669fec0..8f4db67533e 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -113,11 +113,19 @@ static inline void __iomem *__typesafe_io(unsigned long addr) #define __iowmb() do { } while (0) #endif +/* PCI fixed i/o mapping */ +#define PCI_IO_VIRT_BASE 0xfee00000 + +extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); + /* * Now, pick up the machine-defined IO definitions */ #ifdef CONFIG_NEED_MACH_IO_H #include +#elif defined(CONFIG_PCI) +#define IO_SPACE_LIMIT ((resource_size_t)0xfffff) +#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) #else #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) #endif diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index a6efcdd6fd2..195ac2f9d3d 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -9,6 +9,9 @@ * * Page table mapping constructs and function prototypes */ +#ifndef __ASM_MACH_MAP_H +#define __ASM_MACH_MAP_H + #include struct map_desc { @@ -34,6 +37,8 @@ struct map_desc { #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); +extern void vm_reserve_area_early(unsigned long addr, unsigned long size, + void *caller); struct mem_type; extern const struct mem_type *get_mem_type(unsigned int type); @@ -44,4 +49,7 @@ extern int ioremap_page(unsigned long virt, unsigned long phys, const struct mem_type *mtype); #else #define iotable_init(map,num) do { } while (0) +#define vm_reserve_area_early(a,s,c) do { } while (0) +#endif + #endif diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 26c511fddf8..df818876fa3 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -11,6 +11,7 @@ #ifndef __ASM_MACH_PCI_H #define __ASM_MACH_PCI_H + struct pci_sys_data; struct pci_ops; struct pci_bus; @@ -54,6 +55,15 @@ struct pci_sys_data { */ void pci_common_init(struct hw_pci *); +/* + * Setup early fixed I/O mapping. + */ +#if defined(CONFIG_PCI) +extern void pci_map_io_early(unsigned long pfn); +#else +static inline void pci_map_io_early(unsigned long pfn) {} +#endif + /* * PCI controllers */ diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 25552508c3f..c3165f0fef6 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -13,6 +13,7 @@ #include #include +#include #include static int debug_pci; @@ -627,3 +628,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, return 0; } + +void __init pci_map_io_early(unsigned long pfn) +{ + struct map_desc pci_io_desc = { + .virtual = PCI_IO_VIRT_BASE, + .type = MT_DEVICE, + .length = SZ_64K, + }; + + pci_io_desc.pfn = pfn; + iotable_init(&pci_io_desc, 1); +} diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 4f55f5062ab..8727802f866 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -36,6 +36,7 @@ #include #include +#include #include "mm.h" int ioremap_page(unsigned long virt, unsigned long phys, @@ -383,3 +384,16 @@ void __arm_iounmap(volatile void __iomem *io_addr) arch_iounmap(io_addr); } EXPORT_SYMBOL(__arm_iounmap); + +#ifdef CONFIG_PCI +int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) +{ + BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT); + + return ioremap_page_range(PCI_IO_VIRT_BASE + offset, + PCI_IO_VIRT_BASE + offset + SZ_64K, + phys_addr, + __pgprot(get_mem_type(MT_DEVICE)->prot_pte)); +} +EXPORT_SYMBOL_GPL(pci_ioremap_io); +#endif diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index cf4528d5177..714a7fd99ca 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -31,6 +31,7 @@ #include #include +#include #include "mm.h" @@ -216,7 +217,7 @@ static struct mem_type mem_types[] = { .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, .domain = DOMAIN_IO, - }, + }, [MT_DEVICE_WC] = { /* ioremap_wc */ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, .prot_l1 = PMD_TYPE_TABLE, @@ -783,14 +784,27 @@ void __init iotable_init(struct map_desc *io_desc, int nr) create_mapping(md); vm->addr = (void *)(md->virtual & PAGE_MASK); vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); - vm->phys_addr = __pfn_to_phys(md->pfn); - vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; + vm->phys_addr = __pfn_to_phys(md->pfn); + vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; vm->flags |= VM_ARM_MTYPE(md->type); vm->caller = iotable_init; vm_area_add_early(vm++); } } +void __init vm_reserve_area_early(unsigned long addr, unsigned long size, + void *caller) +{ + struct vm_struct *vm; + + vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); + vm->addr = (void *)addr; + vm->size = size; + vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; + vm->caller = caller; + vm_area_add_early(vm); +} + #ifndef CONFIG_ARM_LPAE /* @@ -808,14 +822,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr) static void __init pmd_empty_section_gap(unsigned long addr) { - struct vm_struct *vm; - - vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); - vm->addr = (void *)addr; - vm->size = SECTION_SIZE; - vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; - vm->caller = pmd_empty_section_gap; - vm_area_add_early(vm); + vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); } static void __init fill_pmd_gaps(void) @@ -864,6 +871,28 @@ static void __init fill_pmd_gaps(void) #define fill_pmd_gaps() do { } while (0) #endif +#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) +static void __init pci_reserve_io(void) +{ + struct vm_struct *vm; + unsigned long addr; + + /* we're still single threaded hence no lock needed here */ + for (vm = vmlist; vm; vm = vm->next) { + if (!(vm->flags & VM_ARM_STATIC_MAPPING)) + continue; + addr = (unsigned long)vm->addr; + addr &= ~(SZ_2M - 1); + if (addr == PCI_IO_VIRT_BASE) + return; + + } + vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); +} +#else +#define pci_reserve_io() do { } while (0) +#endif + static void * __initdata vmalloc_min = (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); @@ -1147,6 +1176,9 @@ static void __init devicemaps_init(struct machine_desc *mdesc) mdesc->map_io(); fill_pmd_gaps(); + /* Reserve fixed i/o space in VMALLOC region */ + pci_reserve_io(); + /* * Finally flush the caches and tlb to ensure that we're in a * consistent state wrt the writebuffer. This also ensures that -- cgit v1.2.3 From 3c5d1699887bfcd17e6d9842ba7e2b3234e665db Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 9 Jul 2012 21:59:03 -0500 Subject: ARM: move PCI i/o resource setup into common code With consolidation of the PCI i/o mappings, the i/o space is being set to start at a PCI bus addr of 0x0 and fixed to 64K per bus. In this case the core ARM PCI setup code can setup the i/o resource. Currently, the resource is only setup if the platform did not setup an i/o resource. Signed-off-by: Rob Herring Reviewed-by: Arnd Bergmann --- arch/arm/include/asm/mach/pci.h | 3 +++ arch/arm/kernel/bios32.c | 41 ++++++++++++++++++++++++++++++++++++----- 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index df818876fa3..db9fedb57f2 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -11,6 +11,7 @@ #ifndef __ASM_MACH_PCI_H #define __ASM_MACH_PCI_H +#include struct pci_sys_data; struct pci_ops; @@ -43,6 +44,8 @@ struct pci_sys_data { unsigned long io_offset; /* bus->cpu IO mapping offset */ struct pci_bus *bus; /* PCI bus */ struct list_head resources; /* root bus resources (apertures) */ + struct resource io_res; + char io_res_name[12]; /* Bridge swizzling */ u8 (*swizzle)(struct pci_dev *, u8 *); /* IRQ mapping */ diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index c3165f0fef6..036f7ea5812 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -424,6 +424,38 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } +static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys) +{ + int ret; + struct pci_host_bridge_window *window; + + if (list_empty(&sys->resources)) { + pci_add_resource_offset(&sys->resources, + &iomem_resource, sys->mem_offset); + } + + list_for_each_entry(window, &sys->resources, list) { + if (resource_type(window->res) == IORESOURCE_IO) + return 0; + } + + sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; + sys->io_res.end = (busnr + 1) * SZ_64K - 1; + sys->io_res.flags = IORESOURCE_IO; + sys->io_res.name = sys->io_res_name; + sprintf(sys->io_res_name, "PCI%d I/O", busnr); + + ret = request_resource(&ioport_resource, &sys->io_res); + if (ret) { + pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); + return ret; + } + pci_add_resource_offset(&sys->resources, &sys->io_res, + sys->io_offset); + + return 0; +} + static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) { struct pci_sys_data *sys = NULL; @@ -446,11 +478,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) ret = hw->setup(nr, sys); if (ret > 0) { - if (list_empty(&sys->resources)) { - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); - pci_add_resource_offset(&sys->resources, - &iomem_resource, sys->mem_offset); + ret = pcibios_init_resources(nr, sys); + if (ret) { + kfree(sys); + break; } if (hw->scan) -- cgit v1.2.3 From fe5051754263e7198aa8f415b2e1298c126adb4e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Sun, 8 Jul 2012 22:13:54 -0500 Subject: ARM: versatile: use fixed PCI i/o mapping Move versatile PCI to fixed i/o mapping and remove io.h. Signed-off-by: Rob Herring Cc: Russell King Cc: Linus Walleij Reviewed-by: Arnd Bergmann --- arch/arm/Kconfig | 1 - arch/arm/mach-versatile/core.c | 5 ----- arch/arm/mach-versatile/include/mach/hardware.h | 1 - arch/arm/mach-versatile/include/mach/io.h | 27 ------------------------- arch/arm/mach-versatile/pci.c | 22 ++++---------------- 5 files changed, 4 insertions(+), 52 deletions(-) delete mode 100644 arch/arm/mach-versatile/include/mach/io.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a91009c6187..8fb7e4af28e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -293,7 +293,6 @@ config ARCH_VERSATILE select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB - select NEED_MACH_IO_H if PCI select PLAT_VERSATILE select PLAT_VERSATILE_CLCD select PLAT_VERSATILE_FPGA_IRQ diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index cd8ea3588f9..ca7902c6ed1 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -169,11 +169,6 @@ static struct map_desc versatile_io_desc[] __initdata = { .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE), .length = VERSATILE_PCI_CFG_BASE_SIZE, .type = MT_DEVICE - }, { - .virtual = (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0, - .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0), - .length = IO_SPACE_LIMIT, - .type = MT_DEVICE }, #endif }; diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h index 408e58da46c..3e5d425e2a9 100644 --- a/arch/arm/mach-versatile/include/mach/hardware.h +++ b/arch/arm/mach-versatile/include/mach/hardware.h @@ -29,7 +29,6 @@ */ #define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul #define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul -#define VERSATILE_PCI_VIRT_MEM_BASE0 (void __iomem *)PCIO_BASE /* macro to get at MMIO space when running virtually */ #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h deleted file mode 100644 index 0406513be7d..00000000000 --- a/arch/arm/mach-versatile/include/mach/io.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * arch/arm/mach-versatile/include/mach/io.h - * - * Copyright (C) 2003 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define PCIO_BASE 0xeb000000ul - -#define __io(a) ((a) + PCIO_BASE) - -#endif diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index e95bf84cc83..2f84f4094f1 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -169,13 +169,6 @@ static struct pci_ops pci_versatile_ops = { .write = versatile_write_config, }; -static struct resource io_port = { - .name = "PCI", - .start = 0, - .end = IO_SPACE_LIMIT, - .flags = IORESOURCE_IO, -}; - static struct resource io_mem = { .name = "PCI I/O space", .start = VERSATILE_PCI_MEM_BASE0, @@ -207,12 +200,6 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys) "memory region (%d)\n", ret); goto out; } - ret = request_resource(&ioport_resource, &io_port); - if (ret) { - printk(KERN_ERR "PCI: unable to allocate I/O " - "port region (%d)\n", ret); - goto out; - } ret = request_resource(&iomem_resource, &non_mem); if (ret) { printk(KERN_ERR "PCI: unable to allocate non-prefetchable " @@ -227,11 +214,9 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys) } /* - * the IO resource for this bus * the mem resource for this bus * the prefetch mem resource for this bus */ - pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset); pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); @@ -260,9 +245,11 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) goto out; } + ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0); + if (ret) + goto out; + if (nr == 0) { - sys->mem_offset = 0; - sys->io_offset = 0; ret = pci_versatile_setup_resources(sys); if (ret < 0) { printk("pci_versatile_setup: resources... oops?\n"); @@ -319,7 +306,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) void __init pci_versatile_preinit(void) { - pcibios_min_io = 0x44000000; pcibios_min_mem = 0x50000000; __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0); -- cgit v1.2.3 From d94c7a04b84e825b7cdeb112a11935ec0e70afd7 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 13 Jul 2012 16:22:24 -0500 Subject: ARM: tegra: use fixed PCI i/o mapping Move tegra PCI to fixed i/o mapping and remove io.h. Signed-off-by: Rob Herring Cc: Colin Cross Cc: Olof Johansson Acked-by: Stephen Warren Reviewed-by: Arnd Bergmann --- arch/arm/Kconfig | 1 - arch/arm/mach-tegra/include/mach/io.h | 46 ---------------- arch/arm/mach-tegra/include/mach/iomap.h | 3 + arch/arm/mach-tegra/pcie.c | 95 ++++++++------------------------ 4 files changed, 25 insertions(+), 120 deletions(-) delete mode 100644 arch/arm/mach-tegra/include/mach/io.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8fb7e4af28e..ac446e3d802 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -644,7 +644,6 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select NEED_MACH_IO_H if PCI select ARCH_HAS_CPUFREQ help This enables support for NVIDIA Tegra based systems (Tegra APX, diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h deleted file mode 100644 index fe700f9ce7d..00000000000 --- a/arch/arm/mach-tegra/include/mach/io.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/io.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross - * Erik Gilling - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_IO_H -#define __MACH_TEGRA_IO_H - -#define IO_SPACE_LIMIT 0xffff - -#ifndef __ASSEMBLER__ - -#ifdef CONFIG_TEGRA_PCI -extern void __iomem *tegra_pcie_io_base; - -static inline void __iomem *__io(unsigned long addr) -{ - return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT); -} -#else -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} -#endif - -#define __io(a) __io(a) - -#endif - -#endif diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index 7e76da73121..fee3a94c454 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -303,6 +303,9 @@ #define IO_APB_VIRT IOMEM(0xFE300000) #define IO_APB_SIZE SZ_1M +#define TEGRA_PCIE_BASE 0x80000000 +#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M) + #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index 0e09137506e..e483be8c6f0 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -171,8 +171,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); * 0x90000000 - 0x9fffffff - non-prefetchable memory * 0xa0000000 - 0xbfffffff - prefetchable memory */ -#define TEGRA_PCIE_BASE 0x80000000 - #define PCIE_REGS_SZ SZ_16K #define PCIE_CFG_OFF PCIE_REGS_SZ #define PCIE_CFG_SZ SZ_1M @@ -180,8 +178,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); #define PCIE_EXT_CFG_SZ SZ_1M #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) -#define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M) -#define MMIO_SIZE SZ_64K #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) #define MEM_SIZE_0 SZ_128M #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) @@ -204,10 +200,9 @@ struct tegra_pcie_port { bool link_up; - char io_space_name[16]; char mem_space_name[16]; char prefetch_space_name[20]; - struct resource res[3]; + struct resource res[2]; }; struct tegra_pcie_info { @@ -223,17 +218,7 @@ struct tegra_pcie_info { struct clk *pll_e; }; -static struct tegra_pcie_info tegra_pcie = { - .res_mmio = { - .name = "PCI IO", - .start = MMIO_BASE, - .end = MMIO_BASE + MMIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -void __iomem *tegra_pcie_io_base; -EXPORT_SYMBOL(tegra_pcie_io_base); +static struct tegra_pcie_info tegra_pcie; static inline void afi_writel(u32 value, unsigned long offset) { @@ -391,24 +376,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) pp = tegra_pcie.port + nr; pp->root_bus_nr = sys->busnr; - /* - * IORESOURCE_IO - */ - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d I/O", pp->index); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - if (pp->index == 0) { - pp->res[0].start = PCIBIOS_MIN_IO; - pp->res[0].end = pp->res[0].start + SZ_32K - 1; - } else { - pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K; - pp->res[0].end = IO_SPACE_LIMIT; - } - pp->res[0].flags = IORESOURCE_IO; - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE); /* * IORESOURCE_MEM @@ -416,18 +384,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d MEM", pp->index); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; + pp->res[0].name = pp->mem_space_name; if (pp->index == 0) { - pp->res[1].start = MEM_BASE_0; - pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1; + pp->res[0].start = MEM_BASE_0; + pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1; } else { - pp->res[1].start = MEM_BASE_1; - pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1; + pp->res[0].start = MEM_BASE_1; + pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1; } - pp->res[1].flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res[1])) + pp->res[0].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[0])) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset); /* * IORESOURCE_MEM | IORESOURCE_PREFETCH @@ -435,18 +403,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), "PCIe %d PREFETCH MEM", pp->index); pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; - pp->res[2].name = pp->prefetch_space_name; + pp->res[1].name = pp->prefetch_space_name; if (pp->index == 0) { - pp->res[2].start = PREFETCH_MEM_BASE_0; - pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1; + pp->res[1].start = PREFETCH_MEM_BASE_0; + pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1; } else { - pp->res[2].start = PREFETCH_MEM_BASE_1; - pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1; + pp->res[1].start = PREFETCH_MEM_BASE_1; + pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1; } - pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - if (request_resource(&iomem_resource, &pp->res[2])) + pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe Prefetch Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); return 1; } @@ -541,8 +509,8 @@ static void tegra_pcie_setup_translations(void) /* Bar 2: downstream IO bar */ fpci_bar = ((__u32)0xfdfc << 16); - size = MMIO_SIZE; - axi_address = MMIO_BASE; + size = SZ_128K; + axi_address = TEGRA_PCIE_IO_BASE; afi_writel(axi_address, AFI_AXI_BAR2_START); afi_writel(size >> 12, AFI_AXI_BAR2_SZ); afi_writel(fpci_bar, AFI_FPCI_BAR2); @@ -776,7 +744,6 @@ static void tegra_pcie_clocks_put(void) static int __init tegra_pcie_get_resources(void) { - struct resource *res_mmio = &tegra_pcie.res_mmio; int err; err = tegra_pcie_clocks_get(); @@ -798,34 +765,16 @@ static int __init tegra_pcie_get_resources(void) goto err_map_reg; } - err = request_resource(&iomem_resource, res_mmio); - if (err) { - pr_err("PCIE: Failed to request resources: %d\n", err); - goto err_req_io; - } - - tegra_pcie_io_base = ioremap_nocache(res_mmio->start, - resource_size(res_mmio)); - if (tegra_pcie_io_base == NULL) { - pr_err("PCIE: Failed to map IO\n"); - err = -ENOMEM; - goto err_map_io; - } - err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, IRQF_SHARED, "PCIE", &tegra_pcie); if (err) { pr_err("PCIE: Failed to register IRQ: %d\n", err); - goto err_irq; + goto err_req_io; } set_irq_flags(INT_PCIE_INTR, IRQF_VALID); return 0; -err_irq: - iounmap(tegra_pcie_io_base); -err_map_io: - release_resource(&tegra_pcie.res_mmio); err_req_io: iounmap(tegra_pcie.regs); err_map_reg: -- cgit v1.2.3 From 68ef63227b131a83732753f9fcd258319c37c1c3 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 13 Jul 2012 16:27:22 -0500 Subject: ARM: integrator: use fixed PCI i/o mapping Move integrator PCI to fixed i/o mapping and remove io.h. Signed-off-by: Rob Herring Cc: Russell King Cc: Linus Walleij Reviewed-by: Arnd Bergmann --- arch/arm/Kconfig | 1 - arch/arm/mach-integrator/include/mach/io.h | 33 ------------------------ arch/arm/mach-integrator/include/mach/platform.h | 4 +++ arch/arm/mach-integrator/integrator_ap.c | 9 +++---- arch/arm/mach-integrator/pci_v3.c | 4 --- 5 files changed, 7 insertions(+), 44 deletions(-) delete mode 100644 arch/arm/mach-integrator/include/mach/io.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ac446e3d802..5d376283b7a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -261,7 +261,6 @@ config ARCH_INTEGRATOR select GENERIC_CLOCKEVENTS select PLAT_VERSATILE select PLAT_VERSATILE_FPGA_IRQ - select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ select MULTI_IRQ_HANDLER diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h deleted file mode 100644 index 8de70de3dd0..00000000000 --- a/arch/arm/mach-integrator/include/mach/io.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-integrator/include/mach/io.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -/* - * WARNING: this has to mirror definitions in platform.h - */ -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_CONFIG_VADDR 0xec000000 -#define PCI_V3_VADDR 0xed000000 -#define PCI_IO_VADDR 0xee000000 - -#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) - -#endif diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index ec467baade0..4c034752685 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -324,6 +324,10 @@ */ #define PHYS_PCI_V3_BASE 0x62000000 +#define PCI_MEMORY_VADDR 0xe8000000 +#define PCI_CONFIG_VADDR 0xec000000 +#define PCI_V3_VADDR 0xed000000 + /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index c857501c578..fd3bdf8f722 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include @@ -72,7 +73,7 @@ * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) - * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) + * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers @@ -146,11 +147,6 @@ static struct map_desc ap_io_desc[] __initdata = { .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), .length = SZ_64K, .type = MT_DEVICE - }, { - .virtual = PCI_IO_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE), - .length = SZ_64K, - .type = MT_DEVICE } }; @@ -158,6 +154,7 @@ static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); vga_base = PCI_MEMORY_VADDR; + pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); } #define INTEGRATOR_SC_VALID_INT 0x003fffff diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index b866880e82a..3a1305ba9ac 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -374,12 +374,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys) } /* - * the IO resource for this bus * the mem resource for this bus * the prefetch mem resource for this bus */ - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); @@ -498,7 +495,6 @@ void __init pci_v3_preinit(void) unsigned int temp; int ret; - pcibios_min_io = 0x6000; pcibios_min_mem = 0x00100000; /* -- cgit v1.2.3 From 29d396047939c559dc1fd42f2d43fd6006082b07 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 13 Jul 2012 16:27:43 -0500 Subject: ARM: integrator: remove trailing whitespace on pci_v3.c No functional changes. Signed-off-by: Rob Herring Reviewed-by: Arnd Bergmann --- arch/arm/mach-integrator/pci_v3.c | 46 +++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index 3a1305ba9ac..495f181fc93 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -41,61 +41,61 @@ /* * The V3 PCI interface chip in Integrator provides several windows from * local bus memory into the PCI memory areas. Unfortunately, there - * are not really enough windows for our usage, therefore we reuse + * are not really enough windows for our usage, therefore we reuse * one of the windows for access to PCI configuration space. The * memory map is as follows: - * + * * Local Bus Memory Usage - * + * * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable * 60000000 - 60FFFFFF PCI IO. 16M * 61000000 - 61FFFFFF PCI Configuration. 16M - * + * * There are three V3 windows, each described by a pair of V3 registers. * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. * Base0 and Base1 can be used for any type of PCI memory access. Base2 * can be used either for PCI I/O or for I20 accesses. By default, uHAL * uses this only for PCI IO space. - * + * * Normally these spaces are mapped using the following base registers: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF - * + * * This means that I20 and PCI configuration space accesses will fail. - * When PCI configuration accesses are needed (via the uHAL PCI + * When PCI configuration accesses are needed (via the uHAL PCI * configuration space primitives) we must remap the spaces as follows: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 - * + * * To make this work, the code depends on overlapping windows working. - * The V3 chip translates an address by checking its range within + * The V3 chip translates an address by checking its range within * each of the BASE/MAP pairs in turn (in ascending register number * order). It will use the first matching pair. So, for example, * if the same address is mapped by both LB_BASE0/LB_MAP0 and - * LB_BASE1/LB_MAP1, the V3 will use the translation from + * LB_BASE1/LB_MAP1, the V3 will use the translation from * LB_BASE0/LB_MAP0. - * + * * To allow PCI Configuration space access, the code enlarges the * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can * be remapped for use by configuration cycles. - * - * At the end of the PCI Configuration space accesses, + * + * At the end of the PCI Configuration space accesses, * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to * reveal the now restored LB_BASE1/LB_MAP1 window. - * + * * NOTE: We do not set up I2O mapping. I suspect that this is only * for an intelligent (target) device. Using I2O disables most of * the mappings into PCI memory. @@ -127,8 +127,8 @@ * * returns: configuration address to play on the PCI bus * - * To generate the appropriate PCI configuration cycles in the PCI - * configuration address space, you present the V3 with the following pattern + * To generate the appropriate PCI configuration cycles in the PCI + * configuration address space, you present the V3 with the following pattern * (which is very nearly a type 1 (except that the lower two bits are 00 and * not 01). In order for this mapping to work you need to set up one of * the local to PCI aperatures to 16Mbytes in length translating to @@ -138,7 +138,7 @@ * * Type 0: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| @@ -150,7 +150,7 @@ * * Type 1: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| @@ -161,7 +161,7 @@ * 15:11 Device number (5 bits) * 10:8 function number * 7:2 register number - * + * */ static DEFINE_RAW_SPINLOCK(v3_lock); -- cgit v1.2.3 From c04dc9a6bfe88b8c15bf8dd298fc24d6b9df3f22 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 28 Feb 2012 13:15:43 -0600 Subject: ARM: shark: use fixed PCI i/o mapping Convert shark to use the fixed i/o mapping and remove io.h. This shrinks the mapping from 256MB to 1MB, but nothing is using that much space AFAICT. Signed-off-by: Rob Herring Cc: Russell King Reviewed-by: Arnd Bergmann --- arch/arm/Kconfig | 1 - arch/arm/mach-shark/core.c | 18 ------------------ arch/arm/mach-shark/include/mach/debug-macro.S | 7 ++++--- arch/arm/mach-shark/include/mach/entry-macro.S | 3 ++- arch/arm/mach-shark/include/mach/io.h | 18 ------------------ arch/arm/mach-shark/pci.c | 5 +++++ 6 files changed, 11 insertions(+), 41 deletions(-) delete mode 100644 arch/arm/mach-shark/include/mach/io.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5d376283b7a..3dfc555219b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -869,7 +869,6 @@ config ARCH_SHARK select PCI select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H - select NEED_MACH_IO_H help Support for the StrongARM based Digital DNARD machine, also known as "Shark" (). diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c index 2704bcd869c..d35b94ef73b 100644 --- a/arch/arm/mach-shark/core.c +++ b/arch/arm/mach-shark/core.c @@ -21,9 +21,6 @@ #include #include -#define IO_BASE 0xe0000000 -#define IO_SIZE 0x08000000 -#define IO_START 0x40000000 #define ROMCARD_SIZE 0x08000000 #define ROMCARD_START 0x10000000 @@ -104,20 +101,6 @@ arch_initcall(shark_init); extern void shark_init_irq(void); -static struct map_desc shark_io_desc[] __initdata = { - { - .virtual = IO_BASE, - .pfn = __phys_to_pfn(IO_START), - .length = IO_SIZE, - .type = MT_DEVICE - } -}; - -static void __init shark_map_io(void) -{ - iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc)); -} - #define IRQ_TIMER 0 #define HZ_TIME ((1193180 + HZ/2) / HZ) @@ -158,7 +141,6 @@ static void shark_init_early(void) MACHINE_START(SHARK, "Shark") /* Maintainer: Alexander Schulz */ .atag_offset = 0x3000, - .map_io = shark_map_io, .init_early = shark_init_early, .init_irq = shark_init_irq, .timer = &shark_timer, diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S index 20eb2bf2a42..d129119a3f6 100644 --- a/arch/arm/mach-shark/include/mach/debug-macro.S +++ b/arch/arm/mach-shark/include/mach/debug-macro.S @@ -12,9 +12,10 @@ */ .macro addruart, rp, rv, tmp - mov \rp, #0xe0000000 - orr \rp, \rp, #0x000003f8 - mov \rv, \rp + mov \rp, #0x3f8 + orr \rv, \rp, #0xfe000000 + orr \rv, \rv, #0x00e00000 + orr \rp, \rp, #0x40000000 .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S index 5901b09fc96..c9e49f04953 100644 --- a/arch/arm/mach-shark/include/mach/entry-macro.S +++ b/arch/arm/mach-shark/include/mach/entry-macro.S @@ -8,7 +8,8 @@ * warranty of any kind, whether express or implied. */ .macro get_irqnr_preamble, base, tmp - mov \base, #0xe0000000 + mov \base, #0xfe000000 + orr \base, \base, #0x00e00000 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h deleted file mode 100644 index 1a45fc01ff1..00000000000 --- a/arch/arm/mach-shark/include/mach/io.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/io.h - * - * by Alexander Schulz - * - * derived from: - * arch/arm/mach-ebsa110/include/mach/io.h - * Copyright (C) 1997,1998 Russell King - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) ((void __iomem *)(0xe0000000 + (a))) - -#endif diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c index 9089407d532..b8b4ab323a3 100644 --- a/arch/arm/mach-shark/pci.c +++ b/arch/arm/mach-shark/pci.c @@ -8,12 +8,15 @@ #include #include #include +#include #include